Multilevel memory bus system for solid-state mass storage
First Claim
1. A multilevel memory bus system for a solid-state storage device that includes a plurality of semiconductor memory devices, a host interface, at least one flash-specific-DMA controller, and a local processing system that includes a local memory, the multilevel memory bus system comprising:
- an intermediate bus disposed to couple to said at least one flash-specific DMA controller;
a first flash memory bus disposed to couple to at least one semiconductor memory device from the plurality of semiconductor memory devices, said at least one semiconductor memory device including a first semiconductor memory device;
a first flash buffer circuit coupled to said intermediate bus and to said first flash memory bus; and
wherein said intermediate bus is disposed to transfer data at a first data path transfer rate, said first flash memory bus is disposed to transfer data at a second data path transfer rate, and said first and second data path transfer rates are different;
a first output that provides a first data path clock signal having a first clock frequency;
a second output that provides a second data path clock signal having a second clock frequency; and
said first clock frequency is at least equal to said second clock frequency;
said intermediate bus includes a first data path having a first bus width;
said first flash buffer circuit includes a first intermediate bus interface having an interface data throughput that is proportional to said first bus width, said first clock frequency, and a selected sampling rate;
a strobe output disposed to provide a first strobe signal having a first strobe frequency;
wherein said selected sampling rate is at least same as that of said first strobe frequency;
wherein said intermediate bus interface has an interface data throughput that is defined by;
IBthru=DataWidth IB*FREQfactor*FREQ*DS where said IBthru is equal to said interface data throughput, said DataWidth IB is equal to said first bus width, said FREQfactor is equal to the quotient of said first frequency divided by said second clock frequency rounded to the nearest integer, said FREQ is equal to said first clock frequency, and said DS is equal to said selected integer multiple.
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Accused Products
Abstract
The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.
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Citations
29 Claims
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1. A multilevel memory bus system for a solid-state storage device that includes a plurality of semiconductor memory devices, a host interface, at least one flash-specific-DMA controller, and a local processing system that includes a local memory, the multilevel memory bus system comprising:
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an intermediate bus disposed to couple to said at least one flash-specific DMA controller; a first flash memory bus disposed to couple to at least one semiconductor memory device from the plurality of semiconductor memory devices, said at least one semiconductor memory device including a first semiconductor memory device; a first flash buffer circuit coupled to said intermediate bus and to said first flash memory bus; and wherein said intermediate bus is disposed to transfer data at a first data path transfer rate, said first flash memory bus is disposed to transfer data at a second data path transfer rate, and said first and second data path transfer rates are different; a first output that provides a first data path clock signal having a first clock frequency; a second output that provides a second data path clock signal having a second clock frequency; and said first clock frequency is at least equal to said second clock frequency; said intermediate bus includes a first data path having a first bus width; said first flash buffer circuit includes a first intermediate bus interface having an interface data throughput that is proportional to said first bus width, said first clock frequency, and a selected sampling rate; a strobe output disposed to provide a first strobe signal having a first strobe frequency; wherein said selected sampling rate is at least same as that of said first strobe frequency; wherein said intermediate bus interface has an interface data throughput that is defined by; IBthru=DataWidth IB*FREQfactor*FREQ*DS where said IBthru is equal to said interface data throughput, said DataWidth IB is equal to said first bus width, said FREQfactor is equal to the quotient of said first frequency divided by said second clock frequency rounded to the nearest integer, said FREQ is equal to said first clock frequency, and said DS is equal to said selected integer multiple. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 28)
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16. A storage device, comprising:
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a local processing system that includes a local memory, a local bus, at least one flash-specific DMA controller, including a first flash-specific DMA controller, and a host interface; an intermediate bus coupled to said at least one flash-specific DMA controller; a plurality of semiconductor memory devices, including a first semiconductor memory device; a first flash memory bus coupled to said first semiconductor device; a first flash buffer circuit coupled to said intermediate bus and to said first memory bus; and an adaptability mechanism disposed to transfer data across said intermediate bus at a first data path transfer rate and across said first memory bus at a second data path transfer rate that is different from said first data path transfer rate; said intermediate bus includes a first data path having a first bus width; said first flash buffer circuit includes a first intermediate bus interface having an interface data throughput that is proportional to said first bus width, a first clock frequency, and a selected sampling rate; a strobe output disposed to provide a first strobe signal having a first strobe frequency; wherein said selected sampling rate is equal to a selected multiple of said first strobe frequency; wherein said interface data throughput is defined by;
IBthru ;
DPWib*FREQfactor*FREQ* DS where said IBthru is equal to said interface data throughput, said DPWib is equal to said first bus width, said FREQfactor is equal to the quotient of said first frequency divided by said second clock frequency rounded to the nearest integer;said FREQ is equal to said second clock frequency, and said DS is equal to said selected integer multiple. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29)
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Specification