State-monitoring memory element
First Claim
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1. A system, comprising:
- a first circuit comprising memory elements of a memory array that are powered at an input supply voltage, wherein the input supply voltage changes over time; and
a second circuit coupled to a state-monitoring memory element of the memory array, the state-monitoring memory element being representative of a voltage sensitivity of other memory elements of the memory array, wherein the second circuit is configured to determine when the input supply voltage drops below a threshold voltage at which the state-monitory memory element operates, and wherein the second circuit comprises a circuit to provide a degraded ground to the state-monitoring memory element.
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Abstract
Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be disturbed in different locations on the IC for better coverage.
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Citations
17 Claims
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1. A system, comprising:
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a first circuit comprising memory elements of a memory array that are powered at an input supply voltage, wherein the input supply voltage changes over time; and a second circuit coupled to a state-monitoring memory element of the memory array, the state-monitoring memory element being representative of a voltage sensitivity of other memory elements of the memory array, wherein the second circuit is configured to determine when the input supply voltage drops below a threshold voltage at which the state-monitory memory element operates, and wherein the second circuit comprises a circuit to provide a degraded ground to the state-monitoring memory element.
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2. A system, comprising;
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a first circuit comprising memory elements of a memory array that are powered at an input supply voltage, wherein the input supply voltage changes over time; and a second circuit coupled to a state-monitoring memory element of the memory array, the state-monitoring memory element being representative of a voltage sensitivity of other memory elements of memory array, the second circuit is configured to determine when the input supply voltage drops below a threshold voltage at which the state-monitory memory element operates, and wherein the second circuit comprises at least one current source coupled to the state-monitoring memory element.
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3. A system, comprising:
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a first circuit comprising memory elements of a memory array that are powered at an input supply voltage, wherein the input supply voltage changes over time; and a second circuit coupled to a state-monitoring memory element of the memory array, the state-monitoring memory element being representative of a voltage sensitivity of other memory elements of the memory array, wherein the second circuit is configured to determine when the input supply voltage drops below a threshold voltage at which the state-monitory memory element operates, wherein the second circuit is configured to detect when the input supply voltage drops below the threshold voltage and to issue a reset signal responsive to the input supply voltage drop. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system, comprising:
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a first circuit comprising memory elements of a memory array that are powered at an input supply voltage, wherein the input supply voltage changes over time; and a second circuit coupled to a state-monitoring memory element of the memory array, the state-monitoring memory element being representative of a voltage sensitivity of other memory elements of the memory array, wherein the second circuit is configured to determine when the input supply voltage drops below a threshold voltage at which the state-monitory memory element operates, wherein the second circuit further comprises a logic analyzer, wherein the logic analyzer is configured to generate an indicator of failure if the state-monitoring memory element fails to maintain the initial logic state when the input voltage drops below the threshold voltage, and wherein the logic analyzer is adapted to issue a reset signal responsive to detecting a failure in the state-monitoring memory element.
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14. A method, comprising:
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powering a first circuit comprising a memory array of memory elements at an input supply voltage, wherein the input supply voltage changes over time; and determining, using a second circuit comprising a state-monitoring memory element of the memory array, if the input supply voltage drops below a threshold voltage at which the state-monitoring memory element operates, the state-monitoring memory element being representative of a voltage sensitivity of other memory elements of the memory array and the threshold voltage, and wherein the determining comprises providing a degraded ground to the state-monitoring memory element. - View Dependent Claims (15, 16, 17)
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Specification