Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout

• US 8,471,332 B2
• Filed: 01/12/2012
• Issued: 06/25/2013
• Est. Priority Date: 02/11/2005
• Status: Expired due to Fees

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bhalla, Anup, Wang, Xiaobin, Ho, Moses
• Primary Examiner(s): Malsawma, Lex
• Application Number:
  US13/349,288
• Publication Number:
  US 20130009238A1
• Time in Patent Office: 530 Days
• Field of Search: 257/330, 257/334, 257/475, 257/476, 257/484, 257/E27.04, 257/E29.013, 257/E21.616, 438/237
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

Claims

1. A semiconductor power device comprising an active cell area having a plurality of power transistor cells wherein:

each of said power transistor cells is integrated and functioning together with a planar Schottky diode wherein each said active transistor cells comprising a trenched gate surrounded by a body region encompassing a source region of opposite conductivity type therein;

a heavy body region having a body dopant concentration higher than the body region disposed from a top surface of the substrate into the body region adjacent the source region and away from an outer edge of the body region distant from the trenched gate; and

wherein the planar Schottky diode further comprising a Schottky junction barrier metal covering area surrounded by the heavy body region extending over a space between adjacent body regions forming a Schottky diode there between, said adjacent body regions being disposed in a mesa of the semiconductor substrate between two adjacent trenched gate.

2. The semiconductor power device of claim 1 wherein:

a space between adjacent edges of two adjacent body regions is smaller than a space between adjacent edges of two corresponding adjacent heavy body regions.

3. The semiconductor power device of claim 1 wherein:

said heavy body region extends deeper than the source region.

4. The semiconductor power device of claim 1 further comprising:

a Schttoky barrier height adjustment layer on a top portion of the semiconductor substrate in the space between adjacent body regions.

5. The semiconductor power device of claim 4 wherein:

each of said heavy body regions being surrounded by a portion of lightly doped body region between the outer edge of the body region and an outer edge of the heavy body region thus improving a breakdown of the JBS.

6. The semiconductor power device of claim 5 wherein:

said upper source dopant layer with said smaller source dopant concentration than said lower source dopant layer extends in said semiconductor substrate to a depth above a bottom of the body regions of said power transistor cells.

7. The semiconductor power device of claim 1 wherein:

said space between adjacent body regions being narrower than a space between corresponding adjacent heavy body regions each respectively disposed in one of the adjacent body regions.

8. The semiconductor power device of claim 1 wherein:

said power transistor cells further comprising MOSFET transistor cells configured to surround an area of planar Schottky diode with said heavy body regions surrounding the Schottky diode forming Junction Barrier Controlled Schottky (JBS).

9. The semiconductor power device of claim 1 wherein:

said semiconductor substrate comprises an epitaxial layer on an upper portion having a gradually increasing dopant concentration along a vertical direction having a lighter dopant concentration near a top surface of said epitaxial layer.

10. The semiconductor power device of claim 1 wherein:

said body regions are disposed in an upper source dopant layer on top of a lower source dopant layer in said semiconductor substrate and wherein said upper source dopant layer having a smaller dopant concentration than said lower source dopant layer, said upper source dopant layer extends in said substrate to a depth deeper than said heavy body region.

11. The semiconductor power device of claim 1 wherein:

said trenched gate penetrates through a central portion of the source and the body regions into the substrate of source dopant conductivity.