PCI express enhancements and extensions including device window caching
First Claim
1. An apparatus comprising:
- a first input/output (I/O) device adapted to be coupled to a controller hub in a computing system with a serial point-to-point interconnect and adapted to receive input external from the computer system including the first I/O device, the first I/O device including a local memory, wherein a first portion of the local memory is configured to be mapped into a host memory space, which is adapted to be visible to a host processor in the computer system, wherein the first portion of the local memory, when mapped into the host memory space, is to be adapted to be utilized as a window cache for accesses from the host processor to the first I/O device.
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Abstract
A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
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Citations
12 Claims
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1. An apparatus comprising:
a first input/output (I/O) device adapted to be coupled to a controller hub in a computing system with a serial point-to-point interconnect and adapted to receive input external from the computer system including the first I/O device, the first I/O device including a local memory, wherein a first portion of the local memory is configured to be mapped into a host memory space, which is adapted to be visible to a host processor in the computer system, wherein the first portion of the local memory, when mapped into the host memory space, is to be adapted to be utilized as a window cache for accesses from the host processor to the first I/O device. - View Dependent Claims (2, 3, 4)
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5. A system comprising:
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a computer system including a processor, a system memory, a controller hub, and a first I/O device; wherein at least a portion of the system memory is configured to be mapped into a host memory space, which is to be visible to the processor; wherein the first input/output (I/O) device is configured to be coupled to the controller hub through a serial point-to-point interconnect and is adapted to receive data from devices external to the computer system, wherein the first I/O device includes a local memory configured to have at least a portion of the local memory mapped into the host memory space; and wherein the processor is adapted to utilize the portion of the local memory mapped into the host memory space as a window cache for accesses to the first I/O device. - View Dependent Claims (6, 7, 8)
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9. An apparatus comprising:
a first input/output (I/O) device adapted to be coupled to a controller hub in a computing system by a serial point-to-point interconnect, the first I/O device including a local memory, wherein a first portion of the local memory is configured to be mapped into a host memory space, which is adapted to be visible to a host processor in the computer system, wherein the first portion of the local memory, when mapped into the host memory space, is to be adapted to be utilized as a window cache for accesses from the host processor to the first I/O device, and wherein the first I/O device is to be selected from a group consisting of a Network Interface Card (NIC), a graphics card, a graphics accelerator, a graphics processor, a video processor, a network processor, an audio processor, and an external bus device. - View Dependent Claims (10, 11, 12)
Specification