PCI express enhancements and extensions including device window caching

• US 8,473,642 B2
• Filed: 08/04/2011
• Issued: 06/25/2013
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Harriman, David, Rosenbluth, Mark, Bhatt, Ajay, Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert, Falik, Ohad, Mendelson, Abraham, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): MARTINEZ, DAVID E
• Application Number:
  US13/198,559
• Publication Number:
  US 20120036293A1
• Time in Patent Office: 691 Days
• Field of Search: None
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

a first input/output (I/O) device adapted to be coupled to a controller hub in a computing system with a serial point-to-point interconnect and adapted to receive input external from the computer system including the first I/O device, the first I/O device including a local memory, wherein a first portion of the local memory is configured to be mapped into a host memory space, which is adapted to be visible to a host processor in the computer system, wherein the first portion of the local memory, when mapped into the host memory space, is to be adapted to be utilized as a window cache for accesses from the host processor to the first I/O device.

2. The apparatus of claim 1, wherein the first I/O device also includes a Base Address Register (BAR) to store a base address, and wherein a second portion of the local memory is to be mapped as a device address space in the host memory space based on the base address stored in the BAR, the device address space to include the window cache.

3. The apparatus of claim 1, wherein the first device also includes a snoop filter, the snoop filter to track a first number of lines of the local memory that are cached and to filter snoops to a second number of lines of the local memory that are not cached.

4. The apparatus of claim 1, wherein the first device is a Peripheral Component Interconnect Express (PCIE) device.

5. A system comprising:

a computer system including a processor, a system memory, a controller hub, and a first I/O device;

wherein at least a portion of the system memory is configured to be mapped into a host memory space, which is to be visible to the processor;

wherein the first input/output (I/O) device is configured to be coupled to the controller hub through a serial point-to-point interconnect and is adapted to receive data from devices external to the computer system, wherein the first I/O device includes a local memory configured to have at least a portion of the local memory mapped into the host memory space; and

wherein the processor is adapted to utilize the portion of the local memory mapped into the host memory space as a window cache for accesses to the first I/O device.

6. The apparatus of claim 5, wherein the first I/O device also includes a Base Address Register (BAR) to store a base address, and wherein a second portion of the local memory is to be mapped as a device address space in the host memory space based on the base address stored in the BAR, the device address space to include the window cache.

7. The apparatus of claim 5, wherein the first device also includes a snoop filter, the snoop filter to track a first number of lines of the local memory that are cached and to filter snoops to a second number of lines of the local memory that are not cached.

8. The apparatus of claim 5, wherein the first device is a Peripheral Component Interconnect Express (PCIE) device.

9. An apparatus comprising:

a first input/output (I/O) device adapted to be coupled to a controller hub in a computing system by a serial point-to-point interconnect, the first I/O device including a local memory, wherein a first portion of the local memory is configured to be mapped into a host memory space, which is adapted to be visible to a host processor in the computer system, wherein the first portion of the local memory, when mapped into the host memory space, is to be adapted to be utilized as a window cache for accesses from the host processor to the first I/O device, and wherein the first I/O device is to be selected from a group consisting of a Network Interface Card (NIC), a graphics card, a graphics accelerator, a graphics processor, a video processor, a network processor, an audio processor, and an external bus device.

10. The apparatus of claim 9, wherein the first I/O device also includes a Base Address Register (BAR) to store a base address, and wherein a second portion of the local memory is to be mapped as a device address space in the host memory space based on the base address stored in the BAR, the device address space to include the window cache.

11. The apparatus of claim 9, wherein the first device also includes a snoop filter, the snoop filter to track a first number of lines of the local memory that are cached and to filter snoops to a second number of lines of the local memory that are not cached.

12. The apparatus of claim 9, wherein the first device is a Peripheral Component Interconnect Express (PCIE) device.