Method of manufacture and structure for a trench transistor having a heavy body region

• US 8,476,133 B2
• Filed: 01/11/2010
• Issued: 07/02/2013
• Est. Priority Date: 11/14/1997
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Chau, Duc, Sapp, Steven, Bencuya, Izak, Probst, Dean Edward, Mo, Brian Sze-Ki
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): Garcia, Joannie A
• Application Number:
  US12/685,592
• Publication Number:
  US 20100112767A1
• Time in Patent Office: 1,268 Days
• Field of Search: 438/270, 438/272, 438/301, 438/303, 438/305, 438/306, 438/514, 438/519, 438/526, 438/527, 438/589, 438/96, 438/FOR.188, 257/328, 257/330, 257/331, 257/E27.091, 257/E29.201
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Claims

1. A method of manufacturing a trench transistor comprising:

forming a first trench;

forming a second trench, the first trench and the second trench defining a semiconductor mesa therebetween, a height of the semiconductor mesa defining a depth of the first trench and a depth of the second trench, the semiconductor mesa being of a first conductivity type;

lining the first trench and the second trench with a gate dielectric material;

substantially filling the gate dielectric-lined first trench and the gate dielectric-lined second trench with a conductive material, the conductive material forming a gate electrode of the trench transistor;

forming a doped well in the semiconductor mesa, the doped well having a depth that is less than the depth of the first trench and less than the depth of the second trench, the doped well being of a second conductivity type that is opposite the first conductivity type;

forming a source region within the doped well, the source region having a depth that is less than the depth of the doped well, the source region being of the first conductivity type; and

forming a heavy body structure within the doped well, the heavy body structure including a region of the second conductivity type, a dopant of the second conductivity type in the region of the second conductivity type having a peak concentration at a peak concentration depth, the peak concentration depth being greater than the depth of the source region and less than the depth of the doped well.

2. The method of claim 1, further comprising forming a deep doped region of the second conductivity type, the deep doped region having a depth that is greater than the depth of the first trench and greater than the depth of the second trench.

3. The method of claim 2, wherein the deep doped region is configured as a termination structure of the trench transistor.

4. The method of claim 1, wherein the substantially filling the gate dielectric-lined first trench includes filling the gate dielectric-lined first trench such that a recess is formed at an upper portion of the gate dielectric-lined first trench.

5. The method of claim 1, wherein the forming the heavy body structure includes:

performing a first dopant implant of the first conductivity type at a first energy level and a first dosage to form a first doped portion of the heavy body structure; and

performing a second dopant implant of the first conductivity type at a second energy level and a second dosage to form a second doped portion of the heavy body structure.

6. The method of claim 5, wherein the first implant is performed at approximately the peak concentration depth.

7. The method of claim 5, wherein the first energy level is higher than the second energy level.

8. The method of claim 5, wherein the first dosage is higher than the second dosage.

12. The method of claim 1, further comprising forming a contact area on a top surface of the semiconductor mesa.

13. The method of claim 12, wherein the forming the contact area includes forming source contact regions alternating with heavy body contact regions.

9. The method of claim l, wherein the forming the heavy body structure includes diffusing the dopant of the second conductivity type.

10. The method of claim l, wherein the forming the heavy body structure includes implanting the dopant of the second conductivity type at about the peak concentration depth.

11. The method of claim l, wherein the forming the first trench and the second trench includes patterning and etching a semiconductor material such that the first trench extends in parallel with the second trench along a longitudinal axis.

14. The method of claim l, wherein the forming the heavy body structure includes forming an abrupt junction between the region of the second conductivity type and the doped well.

15. A trench transistor comprising:

a first trench disposed in a semiconductor material;

a second trench disposed in the semiconductor material;

a semiconductor mesa disposed between the first trench and the second trench, a height of the semiconductor mesa defining a depth of the first trench and a depth of the second trench, the semiconductor mesa being of a first conductivity type;

a gate dielectric material disposed on a sidewall of the first trench and a sidewall of the second trench;

a conductive material disposed within the gate dielectric material of the first trench and disposed within the gate dielectric material of the second trench, the conductive material forming a gate electrode of the trench transistor and substantially filling the first trench and the second trench;

a doped well disposed in the semiconductor mesa, the doped well having a depth that is less than the depth of the of the first trench and less than the depth of the second trench, the doped well being of a second conductivity type that is opposite the first conductivity type;

a source region disposed in the doped well, the source region having a depth that is less than the depth of the doped well, the source region being of the first conductivity type; and

a heavy body structure disposed in the doped well, the heavy body structure including a region of the second conductivity type, a dopant of the second conductivity type in the region having a peak concentration at a peak concentration depth, the peak concentration depth being greater than the depth of the source region and less than the depth of the doped well.

16. The trench transistor of claim 15, further comprising a deep doped region of the second conductivity type, the deep doped region having a depth that is greater than the depth of the first trench and greater than the depth of the second trench.

17. The trench transistor of claim 16, wherein the deep doped region is configured as a termination structure of the trench transistor.

18. The trench transistor of claim 15, a drain contact disposed on a bottom surface of the trench transistor.

19. The trench transistor of claim 15, further comprising a contact area disposed on a top surface of the semiconductor mesa.

20. The trench transistor of claim 19, wherein the contact area includes a source contact region and a heavy body contact region.

21. A method of forming a trench transistor, the method comprising:

forming a first trench disposed in a semiconductor material and including a gate electrode insulated by a gate dielectric;

forming a second trench disposed in the semiconductor material, the first trench and the second trench defining a semiconductor mesa, the semiconductor mesa being of a first conductivity type and disposed between the first trench and the second trench;

forming a doped well disposed in the semiconductor mesa, the doped well having a depth less than a depth of the of the first trench and less than a depth of the second trench, the doped well being of a second conductivity type opposite the first conductivity type;

forming a source region having the first conductivity type and disposed in the doped well, the source region having a depth less than the depth of the doped well; and

forming a heavy body region disposed in the doped well, the heavy body region including a region of the second conductivity type, a dopant of the second conductivity type in the region of the second conductivity type having a peak concentration at a peak concentration depth, the peak concentration depth being greater than the depth of the source region and less than the depth of the doped well.

22. The method of claim 21, further comprising forming a deep doped region of the second conductivity type, the deep doped region having a depth that is greater than the depth of the first trench and greater than the depth of the second trench, the deep doped region being configured as a termination structure of the trench transistor.