Semiconductor memory device and method of driving the same
First Claim
1. A semiconductor memory device comprising:
- a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor;
word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column;
bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells arranged in the same row;
a common line extending in the column or the row direction, and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells;
a word line voltage applying circuit that applies a voltage to a word line connected to the memory cell selected as a writing target in the writing of the information stored in the memory element;
a first voltage applying circuit that applies a write voltage to the bit line connected to the selected memory cell; and
a second voltage applying circuit that previously applies an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to applying the write voltage, and that applies the precharge voltage to the common line connected to the selected memory cell while the write voltage is applied to the bit line connected to the selected memory cell.
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Accused Products
Abstract
A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
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Citations
26 Claims
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1. A semiconductor memory device comprising:
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a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor; word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column; bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells arranged in the same row; a common line extending in the column or the row direction, and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells; a word line voltage applying circuit that applies a voltage to a word line connected to the memory cell selected as a writing target in the writing of the information stored in the memory element; a first voltage applying circuit that applies a write voltage to the bit line connected to the selected memory cell; and a second voltage applying circuit that previously applies an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to applying the write voltage, and that applies the precharge voltage to the common line connected to the selected memory cell while the write voltage is applied to the bit line connected to the selected memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor memory device comprising:
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a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor; word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column; bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells arranged in the same row; a common line extending in the column or row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells; a word line voltage applying circuit that applies a voltage to a word line connected to the memory cell selected as a writing target in the writing of the information stored in the memory element; a first voltage applying circuit that applies a write voltage to the bit line connected to the selected memory cell; and a second voltage applying circuit that previously applies an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to application of the write voltage, and that applies the precharge voltage to the common line connected to the selected memory cell while the write voltage is applied to the bit line connected to the selected memory cell, wherein in the writing of the information stored in the memory element, a first writing operation of writing the electrical property of the memory element from a first state to a second state, and a second writing operation of writing the electrical property of the memory element from the second state to the first state are included, and the precharge voltage applied by the second voltage applying circuit in the first writing operation is different from that in the second writing operation. - View Dependent Claims (13, 14)
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15. A method of driving a semiconductor memory device,
the semiconductor memory device including: -
a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor; word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column; bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells arranged in the same row; and a common line extending in the column or the row direction, and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells, the method comprising; in the writing of the information stored in the memory element, a word line voltage applying step of selecting the memory cell that is a writing target and applying a word line voltage to the word line connected to the selected memory cell; a precharging step of previously applying an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to application of a write voltage; and a writing step of applying the write voltage to the bit line connected to the selected memory cell and maintaining the application of the precharge voltage to the common line connected to the selected memory cell during the application of the write voltage. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
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24. A method of driving a semiconductor memory device,
the semiconductor memory device including: -
a memory cell array formed of a plurality of memory cells being arranged in column and row directions in a matrix, each of the plurality of memory cells including a memory element and a cell transistor, the memory element having two input/output terminals and storing information by a difference in an electrical property between the two terminals, in which the stored information is written by applying a voltage between the two terminals, the cell transistor having two input/output terminals and one control terminal, one terminal of the input/output terminals of the memory element being connected to one terminal of the input/output terminals of the cell transistor; word lines extending in the column direction and respectively connecting the control terminals of the cell transistors of the memory cells arranged in the same column; bit lines extending in the row direction and connecting the other terminals of the input/output terminals, which do not connect with the memory elements, of the cell transistors of the memory cells arranged in the same row; and a common line extending in the column or the row direction and connecting the other terminals of the input/output terminals, which do not connect with the cell transistors, of the memory elements of the memory cells, the method comprising; in the writing of the information stored in the memory element, a word line voltage applying step of selecting the memory cell that is a writing target and applying a word line voltage to the word line connected to the selected memory cell; a precharging step of previously applying an identical precharge voltage to both of the bit line and the common line connected to the selected memory cell prior to application of a write voltage; and a writing step of applying the write voltage to the bit line connected to the selected memory cell and maintaining the application of the precharge voltage to the common line connected to the selected memory cell during the application of the write voltage, wherein the precharge voltage applied in the precharging step and the writing step in a case of writing the electrical property of the memory element from a first state to a second state is different from that in a case of writing the electrical property of the memory element from the second state to the first state. - View Dependent Claims (25, 26)
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Specification