Oxide semiconductor film and semiconductor device

• US 8,492,758 B2
• Filed: 09/22/2010
• Issued: 07/23/2013
• Est. Priority Date: 09/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakakura, Masayuki, Watanabe, Ryosuke, Sakata, Junichiro, Akimoto, Kengo, Miyanaga, Akiharu, Hirohashi, Takuya, Kishida, Hideyuki
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US12/887,646
• Publication Number:
  US 20110068335A1
• Time in Patent Office: 1,035 Days
• Field of Search: 257/43, 257/E21.476, 257/E29.296, 438/158
• US Class Current: 257/43
• CPC Class Codes: H01L 21/2636 for heating, e.g. electron beam heating
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

an oxide semiconductor layer comprising a first region and a second region;

a gate insulating layer between the gate electrode layer and the oxide semiconductor layer;

a source electrode layer and a drain electrode layer electrically connected the oxide semiconductor layer; and

an oxide insulating layer in contact with the oxide semiconductor layer,

wherein the oxide semiconductor layer is between the gate insulating layer and the oxide insulating layer,

wherein the first region comprises crystals which are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer, and

wherein the second region is an amorphous region or a region in which amorphousness and microcrystals are mixed.

2. The semiconductor device according to claim 1, wherein a length of a crystal in the first region in the direction of an a-axis or a b-axis is greater than or equal to 2 nm and less than or equal to 50 nm.

3. The semiconductor device according to claim 1, wherein a crystal structure of the crystals in the first region is represented by In₂Ga₂ZnO₇.

4. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer contains In, Ga and Zn, and

wherein a molar ratio of In to Ga to Zn of the second region is 1:

1;

0.5.

5. The semiconductor device according to claim 1, wherein a thickness of the oxide semiconductor layer is greater than or equal to 10 nm and less than or equal to 200 nm.

6. A semiconductor device comprising:

a gate electrode layer over an insulating surface;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, and are over the gate insulating layer; and

an oxide insulating layer in contact with the oxide semiconductor layer, over the source electrode layer and the drain electrode layer,

wherein the oxide semiconductor layer includes a needle crystal group on at least one surface side, the needle crystal group growing in a c-axis direction perpendicular to the surface and having an a-b plane parallel to the surface,

wherein a length of a needle crystal in the needle crystal group in the c-axis direction is greater than or equal to five times as long as a length in a direction of an a-axis or a b-axis, and

wherein a region except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed.

7. The semiconductor device according to claim 6, wherein the length of the needle crystal in the direction of the a-axis or the b-axis is greater than or equal to 2 nm and less than or equal to 50 nm.

8. The semiconductor device according to claim 6, wherein a crystal structure of the needle crystal group is represented by In₂Ga₂ZnO₇.

9. The semiconductor device according to claim 6,

wherein the oxide semiconductor layer contains In, Ga and Zn, and

wherein a molar ratio of In to Ga to Zn in a structure of the amorphous region or the region in which amorphousness and microcrystals are mixed is 1:

1;

0.5.

10. The semiconductor device according to claim 6, wherein a thickness of the oxide semiconductor layer is greater than or equal to 10 nm and less than or equal to 200 nm.

11. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer comprising a first region and a second region and over the gate insulating layer;

a source electrode layer and a drain electrode layer over the gate insulating layer and electrically connected to the oxide semiconductor layer; and

an oxide insulating layer over the source electrode layer and the drain electrode layer,

wherein the oxide insulating layer is in contact with the oxide semiconductor layer,

wherein the first region comprises crystals which are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer, and

wherein the second region includes microcrystals.

12. The semiconductor device according to claim 11, wherein a length of a crystal in the first region in a direction of an a-axis or a b-axis is greater than or equal to 2 nm and less than or equal to 50 nm.

13. The semiconductor device according to claim 11, wherein a crystal structure of the crystals in the first region is represented by In₂Ga₂ZnO₇.

14. The semiconductor device according to claim 11,

wherein the oxide semiconductor layer contains In, Ga and Zn, and

wherein a molar ratio of In to Ga to Zn of the second region is 1:

1;

0.5.

15. The semiconductor device according to claim 11, wherein a thickness of the oxide semiconductor layer is greater than or equal to 10 nm and less than or equal to 200 nm.

16. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer comprising a channel formation region and over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

an oxide insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer and the drain electrode layer; and

a pixel electrode electrically connected to one of the source electrode layer and the drain electrode layer,

wherein the channel formation region comprises crystals which are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

17. The semiconductor device according to claim 16, wherein the oxide semiconductor layer contains In, Ga and Zn.

18. The semiconductor device according to claim 16, wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

19. The semiconductor device according to claim 16, wherein the entire oxide semiconductor layer overlaps with the gate electrode layer.

20. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer comprising a channel formation region and over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

a first insulating layer over and in contact with the oxide semiconductor layer, the source electrode layer and the drain electrode layer;

a second insulating layer over the first insulating layer,

a third insulating layer over the second insulating layer; and

a pixel electrode over the third insulating layer,

wherein the pixel electrode is electrically connected to one of the source electrode layer and the drain electrode layer,

wherein the first insulating layer comprises silicon oxide,

wherein the second insulating layer comprises silicon nitride, and

wherein the third insulating layer comprises a resin, and

wherein the channel formation region comprises crystals which are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

21. The semiconductor device according to claim 20, wherein the oxide semiconductor layer contains In, Ga and Zn.

22. The semiconductor device according to claim 20, wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

23. The semiconductor device according to claim 20, wherein the entire oxide semiconductor layer overlaps with the gate electrode layer.

24. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer comprising a channel formation region and over the gate insulating layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor layer;

an oxide insulating layer over the oxide semiconductor layer; and

a pixel electrode electrically connected to one of the source electrode layer and the drain electrode layer,

wherein each of the source electrode layer and the drain electrode layer comprises a conductive layer which comprises titanium,

wherein the oxide semiconductor layer comprises a first region in contact with the oxide insulating layer and a second region in contact with the conductive layer,

wherein resistance of the first region is higher than resistance of the second region, and

wherein the channel formation region comprises crystals which are c-axis-oriented in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

25. The semiconductor device according to claim 24, wherein the oxide semiconductor layer contains In, Ga and Zn.

26. The semiconductor device according to claim 24, wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

27. The semiconductor device according to claim 24, wherein the entire oxide semiconductor layer overlaps with the gate electrode layer.