Memory access without internal microprocessor intervention
First Claim
1. A computer system, comprising:
- a sensor panel;
a first device configured to receive and process sense signals from the sensor panel, the first device including a first processor, a first memory and a first communication interface; and
a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first memory without intervention by the first processor;
wherein the access operation comprises storing a boot program from the second memory to the first memory; and
wherein the computer system further comprises;
an attention (ATN) line connecting the first communication interface and the second communication interface; and
a power manager module configured to initiate the access operation by generating a power manager boot request signal and transmitting the power manager boot request signal to the first communication interface,wherein the power manager boot request signal causes a signal on the ATN line to be set to a predetermined state.
3 Assignments
0 Petitions
Accused Products
Abstract
A method and system for accessing a computer system memory without processor intervention is disclosed. In one embodiment, the method includes initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface. The predetermined communication protocol enables an access operation to be performed on the first or second memory without intervention by the first or second processor. In one embodiment, the predetermined communication protocol utilizes a plurality of predefined packet types which are identified by a packet header decoder.
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Citations
46 Claims
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1. A computer system, comprising:
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a sensor panel; a first device configured to receive and process sense signals from the sensor panel, the first device including a first processor, a first memory and a first communication interface; and a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first memory without intervention by the first processor; wherein the access operation comprises storing a boot program from the second memory to the first memory; and wherein the computer system further comprises; an attention (ATN) line connecting the first communication interface and the second communication interface; and a power manager module configured to initiate the access operation by generating a power manager boot request signal and transmitting the power manager boot request signal to the first communication interface, wherein the power manager boot request signal causes a signal on the ATN line to be set to a predetermined state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 45, 46)
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25. A computer system, comprising:
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a first device configured to receive and process signals, the first device including a first processor, a first memory and a first communication interface; and a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first memory without intervention by the first processor; wherein the first communication interface further comprises a bus master interface configured to support execution of the access operation and wherein the access operation comprises at least one of a read operation, a write operation or a read-modify-write operation; wherein the second communication interface is configured to initiate the access operation; and wherein the computer system further comprises; a packet header decoder configured to decode the access operation; and a micro-sequencer configured to execute instructions for the decoded access operation and provide commands to the bus master interface.
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26. A computer system, comprising:
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a first device including a first processor, a first memory and a first communication interface; a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined packet-based communication protocol that utilizes a plurality of packet types each having a predefined header format; a packet header decoder for identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and a logic device contained within the first communication interface configured to be responsive to the packet type and execute an access operation to be performed on the first memory without intervention by the first processor; wherein the access operation comprises storing a boot program from the second memory to the first memory; and wherein the access operation further comprises a read-modify-write operation performed on data stored in the first memory. - View Dependent Claims (27, 28, 29, 30, 31, 32)
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33. A method of accessing a computer system memory, comprising:
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initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface, and using the predetermined communication protocol, enabling an access operation to be performed on the first memory without intervention by the first or second processor; wherein using the predetermined communication protocol includes identifying a packet header for identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and in response to the identified packet type executing an access operation to be performed on the first memory without intervention by the first processor; wherein the access operation comprises storing a boot program from the second memory to the first memory; and wherein the access operation further comprises a read-modify-write operation performed on data stored in the first memory. - View Dependent Claims (34, 35, 36)
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37. A computer system, comprising:
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means for initiating a predetermined communication protocol between a first device and a second device, the first device including a first processor, a first memory and a first communication interface, the second device including a second processor, a second memory and a second communication interface, and wherein the predetermined communication protocol utilizes a plurality of packet types each having a predefined header format and enables an access operation to be performed on the first or second memory without intervention by the first processor; wherein using the predetermined communication protocol includes means for identifying a packet header for identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and in response to the identified packet type means for executing an access operation to be performed on the first memory without intervention by the first processor; wherein the access operation comprises storing a boot program from the second memory to the first memory; and wherein the access operation further corn rises a read-modify-write operation performed on data stored in the first memory. - View Dependent Claims (38, 39, 40, 41)
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42. A mobile telephone, comprising:
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a sensor panel; a first device configured to receive and process sense signals from the sensor panel, the first device including a first processor, a first memory and a first communication interface; and a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first memory without intervention by the first processor; the first communication interface further comprising; a packet header decoder for identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and a logic device configured to be responsive to the packet type and execute an access operation to be performed on the first memory without intervention by the first processor; wherein the access operation comprises storing a boot program from the second memory to the first memory; and wherein the access operation further comprises a read-modify-write operation performed on data stored in the first memory.
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43. A digital audio player, comprising:
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a sensor panel; a first device configured to receive and process sense signals from the sensor panel, the first device including a first processor, a first memory and a first communication interface; and a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first memory without intervention by the first processor; the first communication interface further comprising; a packet header decoder for identifying a packet type corresponding to a packet transmitted between the first and second communication interfaces; and a logic device configured to be responsive to the packet type and execute an access operation to be performed on the first memory without intervention by the first processor; wherein the access operation comprises storing a boot program from the second memory to the first memory; and wherein the access operation further comprises a read-modify-write operation performed on data stored in the first memory.
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44. A computer system, comprising:
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a sensor panel; a first device configured to receive and process sense signals from the sensor panel, the first device including a first processor, a first memory and a first communication interface; and a second device, external to the first device, including a second processor, a second memory and a second communication interface, wherein the first and second devices communicate via the first and second communication interfaces implementing a predetermined communication protocol that enables an access operation to be performed on the first memory without intervention by the first processor; wherein the second communication interface is configured to initiate the access operation by sending a memory read request command to the first communication interface wherein the first communication interface further comprises a bus master interface configured to support execution of the access operation and wherein the access operation comprises the second device reading data stored in the first memory; a packet header decoder configured to decode the access operation; and a micro-sequencer configured to execute instructions for the decoded access operation and provide commands to the bus master interface.
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Specification