Systems and devices including multi-transistor cells and methods of using, making, and operating the same

• US 8,546,876 B2
• Filed: 03/20/2008
• Issued: 10/01/2013
• Est. Priority Date: 03/20/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US12/052,317
• Publication Number:
  US 20090238010A1
• Time in Patent Office: 2,021 Days
• Field of Search: 257/686, 257/242, 257/288, 257/296, 257330-332, 257365-366, 257/401, 257/E27.06, 257/E27.084
• US Class Current: 257/331
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A device may include a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain. Methods, systems, and other devices are contemplated.

Claims

1. A device, comprising:

an upper transistor that is stacked elevationally over a lower transistor, the transistors individually comprising a gate and a channel, the channel of the upper transistor having a depth and the channel of the lower transistor having a depth, the channel depths of the upper and lower transistors having respective portions which overlap laterally relative each other, the gate of the upper transistor crossing over the gate of the lower transistor.

2. The device of claim 1, wherein the channel of the upper transistor has a channel length a portion of which is generally perpendicular to a portion of a channel length of the channel of the lower transistor.

3. The device of claim 1, wherein a portion of the channel of the upper transistor is generally vertical.

4. The device of claim 1, wherein the upper transistor and the lower transistor form an AND gate.

5. The device of claim 1, wherein the upper transistor and the lower transistor form an OR gate.

6. The device of claim 1, wherein a gate of the upper transistor is generally perpendicular to a gate of the lower transistor.

7. The device of claim 1, wherein the lower transistor comprises two gates.

8. The device of claim 1, wherein the upper transistor comprises two gates.

9. The device of claim 1 wherein the upper transistor comprises a pair of spaced vertically elongated conductive channel portions.

10. The device of claim 1 wherein the upper transistor comprises a pair of spaced horizontally elongated conductive channel portions.

11. A device, comprising:

stacked upper and lower transistors which individually comprise a channel, wherein the channel of the upper transistor has a depth and the channel of the lower transistor has a depth, the channel depths of the upper and lower transistors having respective portions which overlap laterally relative each other, the stacked upper and lower transistors comprising a first leg with a doped distal portion and a second leg with a doped distal portion, and wherein the doped distal portion of the second leg is longer than the doped distal portion of the first leg and connects to the channel of the lower transistor.

12. A device, comprising:

stacked upper and lower transistors which individually comprise a channel, wherein the channel of the upper transistor has a depth and the channel of the lower transistor has a depth, the channel depths of the upper and lower transistors having respective portions which overlap laterally relative each other, the upper transistor comprising a pair of spaced legs which comprise a part of the channel of the upper transistor, the spaced legs having respective doped elevationally outermost portions that are elevationally over the channel of the upper transistor.

13. The device of claim 12, wherein the lower transistor comprises a gate extending between the pair of spaced legs.

14. The device of claim 13, wherein the upper transistor comprises a pair of gates disposed on either side of the pair of spaced legs.

15. The device of claim 14 wherein the pair of gates of the upper transistor and the gate of the lower transistor cross perpendicularly.

16. The device of claim 14 wherein the pair of gates of the upper transistor are elongated horizontally and the gate of the lower transistor is elongated horizontally.

17. The device of claim 16 wherein the pair of gates of the upper transistor and the gate of the lower transistor cross perpendicularly.

18. A device, comprising:

stacked upper and lower transistors which individually comprise a channel, wherein the channel of the upper transistor has a depth and the channel of the lower transistor has a depth, the channel depths of the upper and lower transistors having respective portions which overlap laterally relative each other, the lower channel being upwardly U-shaped in lateral cross-section.

19. A device, comprising:

stacked upper and lower transistors which individually comprise a channel, wherein the channel of the upper transistor has a depth and the channel of the lower transistor has a depth, the channel depths of the upper and lower transistors having respective portions which overlap laterally relative each other, the upper transistor comprising a pair of spaced legs which comprise a part of the channel of the upper transistor, the channel of the upper transistor comprising a pair of spaced vertically elongated portions in one of the pair of spaced legs.

20. The device of claim 19 wherein the channel of the upper transistor comprises another pair of spaced vertically elongated conductive channel portions in the other one of the pair of spaced legs.

21. A device, comprising:

stacked upper and lower transistors which individually comprise a channel, wherein the channel of the upper transistor has a depth and the channel of the lower transistor has a depth, the channel depths of the upper and lower transistors having respective portions which overlap laterally relative each other, the upper transistor comprising a pair of spaced and vertically oriented legs which comprise a part of the channel of the upper transistor, the channel of the upper transistor comprising a pair of spaced horizontally elongated portions which project perpendicularly in opposite horizontal directions relative to one of the pair of spaced and vertically oriented legs.

22. The device of claim 21 wherein the channel of the upper transistor comprises another pair of spaced horizontally elongated portions which project perpendicularly in opposite horizontal directions relative to the other one of the pair of spaced and vertically oriented legs.

23. A device, comprising:

stacked upper and lower transistors which individually comprise a channel, wherein the channel of the upper transistor has a depth and the channel of the lower transistor has a depth, the channel depths of the upper and lower transistors having respective portions which overlap laterally relative each other;

the upper transistor comprising a pair of spaced and vertically oriented legs which comprise a part of the channel of the upper transistor, the channel of the upper transistor comprising a pair of spaced vertically elongated portions in one of the pair of spaced and vertically oriented legs; and

the channel of the upper transistor comprising a pair of spaced horizontally elongated portions which project perpendicularly in opposite horizontal directions relative to the one of the pair of spaced and vertically oriented legs.

24. The device of claim 23 wherein,

the channel of the upper transistor comprises another pair of spaced vertically elongated conductive channel portions in the other one of the pair of spaced and vertically oriented legs;

and

the channel of the upper transistor comprises another pair of spaced horizontally elongated portions which project perpendicularly in opposite horizontal directions relative to the other one of the pair of spaced and vertically oriented legs.