Method of designing an application specific probe card test system

• US 8,581,610 B2
• Filed: 06/13/2006
• Issued: 11/12/2013
• Est. Priority Date: 04/21/2004
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A, Chraft, Matthew E, Henson, Roy J
• Primary Examiner(s): NGUYEN, NHA T
• Application Number:
  US11/452,784
• Publication Number:
  US 20060273809A1
• Time in Patent Office: 2,709 Days
• Field of Search: 716 4- 6, 716/136, 714724-728, 714/46, 324/500, 324/754, 324/755, 32475401-75411, 32475501-75511, 324/756.03, 32476201-76203, 702/117
• US Class Current: 324/754.01
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs, even during the test process (2) to generate test vector signals to provide to the ICs, and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.

Claims

1. A method of programming a probe card comprising channel connectors to an external tester configured to control testing of integrated circuits (ICs), the probe card further comprising probes for contacting the ICs, the method comprising:

while the probe card is connected through the channel connectors to the external tester, which is external to the probe card, providing a connection code from a source external to the probe card to a memory on the probe card, the connection code specifying a particular pattern of connections of the channel connectors to the probes;

while the probe card is connected through the channel connectors to the external tester, providing the connection code from the memory on the probe card to a programmable controller on the probe card, wherein inputs of the programmable controller are connected to the channel connectors and outputs of the programmable controller are connected to the probes, the programmable controller being programmable to connect selectively the inputs and the outputs in different patterns; and

while the probe card is connected through the channel connectors to the external tester, in response to the connection code in the memory, the programmable controller selectively establishing within itself a pattern of connections between the inputs and the outputs of the programmable controller that corresponds to the particular pattern specified by the connection code in the memory, wherein the programmable controller selectively connects the channel connectors to the probes in the particular pattern specified by the connection code in the memory,

wherein the programmable controller comprises a programmable switch matrix, the method further comprising partially reconfiguring the programmable switch matrix during testing of the ICs.

2. The method of claim 1, wherein the programmable switch matrix comprises a Field Programmable Gate Array (FPGA).

3. The method of claim 1, wherein the programmable switch matrix comprises at least one of a field programmable gate array (FPGA), a digital signal processor (DSP), and a microprocessor.

4. A method of claim 1 wherein the programmable controller is provided on a daughter card attached to a main PCB of the probe card, the programmable controller providing test signals in a serial manner from the daughter card to the main PCB, the method further comprising:

converting the test signals received from the programmable controller from serial to parallel on the main PCB; and

distributing the test signals to the probes.

5. The method of claim 1, wherein at least part of the connection code is derived from a Computer Aided Design (CAD) system.

6. The method of claim 1, wherein:

the ICs comprise memory devices; and

the programmable controller is further configured to send program and erase voltages to provide the signals for burn-in to the ICs.

7. The method of claim 6, wherein the probe card is configured to only transmit the signals to provide for the burn-in.

8. The method of claim 6, wherein serial test signals are provided to at least one serial port of each of the DUTs.

9. The method of claim 6, wherein the ICs comprise at least one of DRAM, SRAM, SDRAM, MPUs and Flash.

10. The method of claim 1, wherein the programmable switch matrix selectively changes interconnections between ones of the channel connections and ones of the probes in accordance with a change of the connection code.

11. The method of claim 1, wherein the testing comprises the external tester generating test signals, which are provided through the channels to the probe card.

12. The method of claim 11, wherein the testing further comprises the programmable controller controlling provision of the test signals from the channel connectors through the probe card to the probes.