Chip package and manufacturing method thereof

• US 8,592,958 B2
• Filed: 12/08/2011
• Issued: 11/26/2013
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Ko, Dongkyun, Lee, Jung, An, Jaesun
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US13/315,039
• Publication Number:
  US 20120098109A1
• Time in Patent Office: 719 Days
• Field of Search: 257/659, 257/660, 257/E23.114
• US Class Current: 257/660
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 2203/0415 : Small preforms other than balls, e.g. discs, cylinders or pillars
• CPC Class Codes: H05K 3/0032 : of organic insulating material
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Claims

1. A chip package, comprising:

a substrate having an upper surface;

at least one chip disposed on the substrate and electrically connected to the substrate;

a molding compound disposed over the substrate and exposing portions of the substrate upper surface;

an electromagnetic interference (EMI) shield including

a first portion disposed over an upper surface of the molding compound;

a second portion forming a plurality of conductive connectors disposed in spaced through holes circumscribing a lateral periphery of the molding compound, a lateral surface of at least one of the plurality of conductive connectors being concave; and

a third portion disposed over all portions of the substrate upper surface exposed from the molding compound.

2. The chip package of claim 1, wherein the at least one of the conductive connectors extends between the first portion of the EMI shield and the substrate.

3. The chip package of claim 2, wherein the conductive connectors provide a ground path between the first portion and the substrate.

4. The chip package of claim 1, wherein the conductive connectors provide partial EMI shielding.

5. The chip package of claim 1, wherein at least one of the plurality of conductive connectors is semi-cylindrical.

6. The chip package of claim 1, wherein the second portion is also disposed over a lateral surface of the molding compound.

7. The chip package of claim 6, wherein the second portion is coupled to the lateral surface of at least one of the conductive connectors.

8. A semiconductor package comprising:

a substrate having an upper surface;

a chip electrically connected to the substrate;

a package body encapsulating the chip and leaving portions of the substrate upper surface exposed; and

means for electromagnetic interference (EMI) shielding, including

first horizontal shielding means for protecting an upper surface of the package body from EMI;

vertical shielding means for protecting lateral surfaces of the package body from EMI; and

second horizontal shielding means for covering all of the portions of the substrate upper surface exposed from the package body.

9. The semiconductor package of claim 8, wherein the vertical shielding means comprises a plurality of conductive vias disposed about a lateral periphery of the package body.

10. The semiconductor package of claim 9, wherein at least one of the conductive vias extends between the first portion of the EMI shield and the substrate.

11. The semiconductor package of claim 10, wherein the at least one of the conductive vias provides a ground path between the first portion and the substrate.

12. The semiconductor package of claim 9, wherein the conductive vias provide partial EMI shielding.

13. The semiconductor package of claim 10, wherein the at least one of the plurality of conductive vias is semi-cylindrical.

14. The semiconductor package of claim 9, wherein the vertical shielding means is disposed over a lateral surface of the molding compound and is coupled to the conductive vias.

15. The semiconductor package of claim 9, wherein the plurality of conductive vias are oriented at a taper angle with respect to the substrate, and the taper angle is between 60°

-90°

.

16. A chip package, comprising:

a substrate having an upper surface;

at least one chip electrically connected to the substrate;

a molding compound encapsulating the chip and defining a lateral surface the molding compound leaving portions of the substrate upper surface adjacent a periphery thereof exposed;

an electromagnetic interference (EMI) shield including

a first portion disposed over an upper surface of the molding compound;

a second portion circumscribing the chip and including a plurality of conductive connectors spaced from one another, a lateral surface of at least one of the plurality of conductive connectors being recessed from the lateral surface of the molding compound; and

a third portion covering all of the exposed portions of the upper surface of the substrate.

17. The chip package of claim 16, wherein the at least one of the conductive connectors extends between the first portion of the EMI shield and the substrate.

18. The chip package of claim 17, wherein the conductive connectors provide a ground path between the first portion and the substrate.

19. The chip package of claim 16, wherein the conductive connectors provide partial EMI shielding.

20. The chip package of claim 16, wherein at least one of the plurality of conductive connectors is semi-cylindrical.