Write driver circuit for MRAM, MRAM and layout structure thereof
First Claim
1. A write driver circuit for a magnetic random access memory comprising a memory cell array comprising a plurality of magnetic memory cells, each of the magnetic memory cells being connected between a bit line and a source line, a pair of magnetic memory cells adjacent to each other in an extension direction of the bit line is configured to share the source line, the write driver circuit comprising:
- a switching unit connected between a terminal for supplying a positive recording voltage and a terminal for supplying a negative recording voltage, and configured to selectively supply current generated by the positive recording voltage or the negative recording voltage to the bit line connecting the magnetic memory cell according to a write enable signal and a data signal so as to influence the resistance state of the magnetic memory cellwherein an output node of the switching unit is configured to be connected to the bit line.
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Accused Products
Abstract
A write driver circuit for a magnetic random access memory includes a memory cell array including a plurality of magnetic memory cells in which a pair of magnetic memory cells adjacent to each other in a direction of a bit line share a source line, and each magnetic memory cell is connected between the bit line and the source line. The write driver circuit includes a switching unit connected between a terminal for supplying a positive recording voltage and a terminal for supplying a negative recording voltage to selectively supply current generated by the positive recording voltage or the negative recording voltage to the bit line according to a write enable signal and a data signal.
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Citations
17 Claims
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1. A write driver circuit for a magnetic random access memory comprising a memory cell array comprising a plurality of magnetic memory cells, each of the magnetic memory cells being connected between a bit line and a source line, a pair of magnetic memory cells adjacent to each other in an extension direction of the bit line is configured to share the source line, the write driver circuit comprising:
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a switching unit connected between a terminal for supplying a positive recording voltage and a terminal for supplying a negative recording voltage, and configured to selectively supply current generated by the positive recording voltage or the negative recording voltage to the bit line connecting the magnetic memory cell according to a write enable signal and a data signal so as to influence the resistance state of the magnetic memory cell wherein an output node of the switching unit is configured to be connected to the bit line. - View Dependent Claims (2, 3, 4)
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5. A magnetic random access memory (MRAM) comprising one or more bit lines, word lines, and common source lines, the MRAM comprising:
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a memory cell array comprising two or more magnetic memory cells connected between a bit line and a common source line, a pair of magnetic memory cells adjacent to each other in an extension direction of the bit line is configured to share the common source line; and a write driver circuit comprising an output node connected to the bit line, and configured to control a current flow direction in the bit line of the magnetic memory cell, so as to affect the resistant state of the magnetic memory cell. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
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13. A magnetic random access memory, comprising:
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a plurality of bit lines in a first direction; a plurality of word lines in a second direction, wherein the first and second directions are not parallel; a plurality of common source lines aligned in the second direction between a pair of the word lines; and a memory cell array comprising two unit magnetic memory cells, each of which is connected between one of the bit lines and one of the common source lines and is driven by a signal applied to the word line connected to the memory cell, wherein the two unit magnetic memory cells are formed to be adjacent to each other in the first direction, and one of the adjacent magnetic memory cells is connected between any one of the bit lines and any one of the common source lines and the other of the adjacent magnetic memory cells is connected between said any one of the common source lines and said any one of the bit lines. - View Dependent Claims (14, 15, 16, 17)
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Specification