Methods and systems for time keeping in a data processing system
First Claim
1. A data processing system, comprising:
- a processing unit;
an interrupt controller coupled to the processing unit, wherein the interrupt controller is configured to transmit a first interrupt signal to the processing unit, the first-priority interrupt signal to cause at least the processing unit to be powered up from a reduced power state; and
a timer circuit coupled to the interrupt controller;
wherein the processing unit is configured to;
maintain a list, wherein the list includes a plurality of entries of time-related events for a plurality of application programs, wherein the plurality of entries include a respective scheduled time for each time-related event to be performed;
select an entry of the plurality of entries of the list for a given one of the time-related events;
determine a time latency value for the processing unit to power up from a reduced power state;
determine a wake up time for the given one of the time-related events dependent upon the determined time latency value and the respective scheduled time included in the selected entry of the plurality of entries;
store a value into the timer circuit, the value representing the determined wake up time for the time-related event to be performed; and
enter the reduced power state;
wherein the timer circuit is configured to initiate an assertion of the first-priority interrupt signal for the time-related event to be performed as scheduled in response to reaching the determined wake up time while the processing unit is in the reduced power state; and
wherein the processing unit is further configured to;
power up from the reduced power state in response to the assertion of the first interrupt signal; and
execute an application program corresponding to the selected entry for the given one of the time-related events.
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Accused Products
Abstract
Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to cause the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.
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Citations
24 Claims
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1. A data processing system, comprising:
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a processing unit; an interrupt controller coupled to the processing unit, wherein the interrupt controller is configured to transmit a first interrupt signal to the processing unit, the first-priority interrupt signal to cause at least the processing unit to be powered up from a reduced power state; and a timer circuit coupled to the interrupt controller; wherein the processing unit is configured to; maintain a list, wherein the list includes a plurality of entries of time-related events for a plurality of application programs, wherein the plurality of entries include a respective scheduled time for each time-related event to be performed; select an entry of the plurality of entries of the list for a given one of the time-related events; determine a time latency value for the processing unit to power up from a reduced power state; determine a wake up time for the given one of the time-related events dependent upon the determined time latency value and the respective scheduled time included in the selected entry of the plurality of entries; store a value into the timer circuit, the value representing the determined wake up time for the time-related event to be performed; and enter the reduced power state; wherein the timer circuit is configured to initiate an assertion of the first-priority interrupt signal for the time-related event to be performed as scheduled in response to reaching the determined wake up time while the processing unit is in the reduced power state; and wherein the processing unit is further configured to; power up from the reduced power state in response to the assertion of the first interrupt signal; and execute an application program corresponding to the selected entry for the given one of the time-related events. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A data processing system comprising:
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a plurality of hardware subsystems, wherein at least one of the plurality of hardware subsystems includes a processing unit; an interrupt controller coupled to the plurality of hardware subsystems, wherein the interrupt controller is configured to provide a first interrupt signal; and a timing circuit coupled to the interrupt controller; wherein the processing unit is configured to; maintain a list, wherein the list includes a plurality of entries of time-related events for a plurality of application programs, wherein the plurality of entries include a respective scheduled time for each time-related events to be performed; select an entry of the plurality of entries of the list for a given one of the time-related events; determine a time latency value for two or more hardware subsystems of the plurality of hardware subsystems to power up from a reduced power state; determine a wake up time for the given one of the time-related events dependent upon the determined time latency value and the respective scheduled time included in the selected entry for the given one of the time-related events; store the wake up time in the timer circuit; enter the reduced power state; wherein the timing circuit is configured to initiate an assertion of the first interrupt signal for the time-related event to be performed as scheduled in response to reaching the determined wake up time; wherein the processing unit is further configured to exit the reduced power state based on the assertion of the first interrupt signal; and wherein, in response to the processing unit exiting the reduced power state, at least a first one of the plurality of application programs is executed by the processing unit and at least a second one of the plurality of application programs is executed by at least one additional hardware subsystem of the plurality of hardware subsystems. - View Dependent Claims (10, 11, 12, 13)
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14. A machine implemented method comprising:
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maintaining a list, wherein the list includes a plurality of entries, wherein each entry of the plurality of entries includes scheduling information for a respective one of a plurality of application programs wherein the plurality of application programs execute on a plurality of different hardware subsystems including a first processor and a second processor; selecting an entry of the plurality of entries of the list for a given one of the plurality of application programs; determining a time latency value indicative of the time required for the first processor and the second processor to exit from a reduced power state; determining a wake up time for the given one of the plurality of application programs dependent upon the determined time latency value and the scheduling information included in the selected entry of the plurality of entries; storing the wake up time in a timing circuit; entering the reduced power state by the first processor and the second processor; asserting a first interrupt signal in response to the wake up time occurring, wherein the timing circuit initiates the assertion of the first interrupt signal by an interrupt controller; and exiting, by the first processor and the second processor, from the reduced power state responsive to the first interrupt signal; executing, by the first processor, at least a first one of the plurality of application programs responsive to the first processor exiting from the reduced power state; and executing, by the second processor, at least a second one of the plurality of application programs responsive to the second processor exiting from the reduced power state. - View Dependent Claims (15, 16, 17, 18)
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19. A computer-readable storage medium storing executable program instructions which when executed by a computer system, cause the computer system to perform a method comprising:
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maintaining a list, wherein the list includes a plurality of entries, wherein each entry of the plurality of entries includes scheduling information for a respective one of a plurality of application programs wherein the plurality of application programs execute on a plurality of different hardware subsystems including a first processor and a second processor; selecting an entry of the plurality of entries of the list for a given one of the plurality of application programs; determining a time latency value indicative of the time required for the first processor and the second processor to exit from a reduced power state; determining a wake up time for the given one of the plurality of application programs dependent upon the determined time latency value and the scheduling information included in the selected entry of the plurality of entries; storing the wake up time in a timing circuit; entering a reduced power state by the first processor; entering a reduced power state by the second processor; asserting a first interrupt signal in response to the wake up time occurring, wherein the timing circuit initiates the assertion of the first interrupt signal by an interrupt controller; exiting, by the first processor, from the reduced power state responsive to the assertion of the first interrupt signal; exiting, by the second processor, from the reduced power state responsive to the assertion of the first interrupt signal; executing, by the first processor, at least a first one of the plurality of application programs responsive to the first processor exiting from the reduced power state; and executing, by the second processor, at least a second one of the plurality of application programs responsive to the second processor exiting from the reduced power state. - View Dependent Claims (20, 21, 22, 23)
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24. A data processing system comprising:
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means for maintaining a list, wherein the list includes a plurality of entries, wherein each entry of the plurality of entries includes scheduling information for a respective one of a plurality of application programs wherein the plurality of application programs execute on a plurality of different hardware subsystems including a first processor and a second processor, wherein the means for selecting includes the first processor; means for selecting an entry of the plurality of entries of the list for a given one of the plurality of application programs; means for determining a time latency value indicative of the time required for the first processor and the second processor to exit from a reduced power state; means for determining a wake up time for the given one of the plurality of application programs dependent upon the determined time latency value and the scheduling information included in the selected entry of the plurality of entries; means for storing the wake up time in a timing circuit, coupled to the means for determining, in response to the determining, wherein the means for storing includes the first processor; means for entering a reduced power state, wherein the means for entering includes the first processor, and wherein the reduced power state includes a zero voltage state means for entering a reduced power state, wherein the means for entering includes the second processor, and wherein the reduced power state includes a zero voltage state means for asserting a first interrupt signal, coupled to the means for storing, in response to the wake up time occurring, wherein the timing circuit initiates the assertion of the first interrupt signal by an interrupt controller; means for exiting from the reduced power state in response to the first interrupt signal wherein the means for exiting includes the first processor; means for exiting from the reduced power state in response to the first interrupt signal wherein the means for exiting includes the second processor; means for executing at least one of the plurality of application programs, wherein the means for executing includes the first processor; and means for executing at least a second one of the plurality of application programs, wherein the means for executing includes the second processor.
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Specification