Signal processing circuit comprising buffer memory device

• US 8,687,416 B2
• Filed: 12/23/2011
• Issued: 04/01/2014
• Est. Priority Date: 12/28/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US13/336,284
• Publication Number:
  US 20120163071A1
• Time in Patent Office: 830 Days
• Field of Search: 365/174, 365/189.08, 365/230.08, 257/298, 438/238, 438/241
• US Class Current: 365/174
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

It is an object to provide a signal processing circuit for which a complex manufacturing process is not necessary and whose power consumption can be suppressed. In particular, it is an object to provide a signal processing circuit whose power consumption can be suppressed by stopping the power supply for a short time. The signal processing circuit includes a control circuit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from the main memory device or the arithmetic unit in accordance with an instruction from the control unit; the buffer memory device comprises a plurality of memory cells; and the memory cells each include a transistor including an oxide semiconductor in a channel formation region and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor.

Claims

1. A signal processing circuit comprising:

a control unit;

an arithmetic unit; and

a buffer memory device,

wherein the buffer memory device stores data sent from a main memory device or the arithmetic unit in accordance with an instruction from the control unit,

wherein the buffer memory device comprises a plurality of memory cells, and

wherein the memory cells each comprise;

a first word line and a second word line;

a first data line and a second data line;

a first transistor comprising an oxide semiconductor in a channel formation region;

a second transistor; and

a memory element to which charge whose amount depends on a value of the data is supplied via the first transistor,

wherein a gate of the first transistor is electrically connected to the first word line and one of source and drain of the first transistor is electrically connected to the first data line, and

wherein a gate of the second transistor is electrically connected to the second word line, one of source and drain of the second transistor is electrically connected to the second data line, and the other of source and drain of the second transistor is electrically connected to the memory element.

2. The signal processing circuit according to claim 1, wherein an off-state current density of the first transistor is lower than or equal to 100 zA/μ

m.

3. The signal processing circuit according to claim 1, wherein the memory element is a transistor or a capacitor.

4. The signal processing circuit according to claim 1, wherein the oxide semiconductor comprises In, Ga, and Zn.

5. The signal processing circuit according to claim 1, wherein a hydrogen concentration of the channel formation region is lower than 5×

10¹⁸/cm³.

6. The signal processing circuit according to claim 1, wherein the signal processing circuit is an LSI comprising a CPU, a DSP, or a microcomputer.

7. A signal processing circuit comprising:

a control unit;

an arithmetic unit;

a buffer memory device; and

a main memory device,

wherein the buffer memory device stores data sent from the main memory device or the arithmetic unit in accordance with an instruction from the control unit,

wherein the buffer memory device comprises a plurality of memory cells, and

wherein the memory cells each comprise;

a first word line and a second word line;

a first data line and a second data line;

a first transistor comprising an oxide semiconductor in a channel formation region;

a second transistor; and

a memory element to which charge whose amount depends on a value of the data is supplied via the first transistor,

wherein a gate of the first transistor is electrically connected to the first word line and one of source and drain of the first transistor is electrically connected to the first data line, and

wherein a gate of the second transistor is electrically connected to the second word line, one of source and drain of the second transistor is electrically connected to the second data line, and the other of source and drain of the second transistor is electrically connected to the memory element.

8. The signal processing circuit according to claim 7, wherein an off-state current density of the first transistor is lower than or equal to 100 zA/μ

m.

9. The signal processing circuit according to claim 7, wherein the memory element is a transistor or a capacitor.

10. The signal processing circuit according to claim 7, wherein the oxide semiconductor comprises In, Ga, and Zn.

11. The signal processing circuit according to claim 7, wherein a hydrogen concentration of the channel formation region is lower than 5×

10¹⁸/cm³.

12. The signal processing circuit according to claim 7, wherein the signal processing circuit is an LSI comprising a CPU, a DSP, or a microcomputer.

13. A signal processing circuit comprising:

a control unit;

an arithmetic unit; and

a buffer memory device,

wherein the buffer memory device stores data including an instruction sent from a main memory device,

wherein the control unit reads the data from the buffer memory device and controls operations of the arithmetic unit and the buffer memory device in accordance with the instruction,

wherein the buffer memory device comprises a plurality of memory cells, and

wherein the memory cells each comprise;

a first word line and a second word line;

a first data line and a second data line;

a first transistor comprising an oxide semiconductor in a channel formation region;

a second transistor; and

a memory element to which charge whose amount depends on a value of the data is supplied via the first transistor,

wherein a gate of the first transistor is electrically connected to the first word line and one of source and drain of the first transistor is electrically connected to the first data line, and

wherein a gate of the second transistor is electrically connected to the second word line, one of source and drain of the second transistor is electrically connected to the second data line, and the other of source and drain of the second transistor is electrically connected to the memory element.

14. The signal processing circuit according to claim 13, wherein an off-state current density of the first transistor is lower than or equal to 100 zA/μ

m.

15. The signal processing circuit according to claim 13, wherein the memory element is a transistor or a capacitor.

16. The signal processing circuit according to claim 13, wherein the oxide semiconductor comprises In, Ga, and Zn.

17. The signal processing circuit according to claim 13, wherein a hydrogen concentration of the channel formation region is lower than 5×

10¹⁸/cm³.

18. The signal processing circuit according to claim 13, wherein the signal processing circuit is an LSI comprising a CPU, a DSP, or a microcomputer.