Memory system for synchronous data transmission
First Claim
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1. A sub-system comprising:
- a plurality of memory devices comprising a first memory device, wherein a timing for a data burst from each of the plurality of memory devices is provided by a respective, different, data strobe (DQS) signal;
an interface circuit comprising;
a plurality of memory data signal interfaces comprising a first memory data signal interface, a number of the plurality of memory data signal interfaces being equal to a number of the plurality of memory devices, each memory data signal interface including a respective data (DQ) path and a respective data strobe (DQS) path coupled to a corresponding memory device of the plurality of memory devices, wherein the first memory data signal interface is coupled to the first memory device;
a system control signal interface coupled to a memory controller, the system control signal interface configured to receive a first read command from the memory controller;
emulation and command translation logic configured to;
select the first memory data signal interface based on the first read command;
receive a first data burst from the first memory data signal interface, wherein a timing reference for the first data burst is provided by a DQS signal of the first memory device;
delay the first data burst to align a phase difference between the DQS signal of the first memory device and a clock signal of the interface circuit; and
transmit the delayed first data burst to the memory controller; and
initialization and configuration logic configured to;
select the first memory data signal interface;
issue a calibration read command, via the first memory data signal interface, to read test data stored at the first memory device;
receive the test data from the first memory device across the first memory data signal interface;
determine the phase difference between the DQS signal of the first memory device and the clock signal based on a timing of the received test data; and
set a delay within the first memory data signal interface corresponding to the first memory device.
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Abstract
One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.
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Citations
16 Claims
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1. A sub-system comprising:
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a plurality of memory devices comprising a first memory device, wherein a timing for a data burst from each of the plurality of memory devices is provided by a respective, different, data strobe (DQS) signal; an interface circuit comprising; a plurality of memory data signal interfaces comprising a first memory data signal interface, a number of the plurality of memory data signal interfaces being equal to a number of the plurality of memory devices, each memory data signal interface including a respective data (DQ) path and a respective data strobe (DQS) path coupled to a corresponding memory device of the plurality of memory devices, wherein the first memory data signal interface is coupled to the first memory device; a system control signal interface coupled to a memory controller, the system control signal interface configured to receive a first read command from the memory controller; emulation and command translation logic configured to; select the first memory data signal interface based on the first read command; receive a first data burst from the first memory data signal interface, wherein a timing reference for the first data burst is provided by a DQS signal of the first memory device; delay the first data burst to align a phase difference between the DQS signal of the first memory device and a clock signal of the interface circuit; and transmit the delayed first data burst to the memory controller; and initialization and configuration logic configured to; select the first memory data signal interface; issue a calibration read command, via the first memory data signal interface, to read test data stored at the first memory device; receive the test data from the first memory device across the first memory data signal interface; determine the phase difference between the DQS signal of the first memory device and the clock signal based on a timing of the received test data; and set a delay within the first memory data signal interface corresponding to the first memory device. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An interface circuit comprising:
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a plurality of memory data signal interfaces comprising a first memory data signal interface, each memory data signal interface including a respective data (DQ) path and a respective data strobe (DQS) path coupled to a respective, different, memory device; a system control signal interface coupled to a memory controller, the system control signal interface configured to receive a first read command from the memory controller; emulation and command translation logic configured to; select the first memory data signal interface based on the first read command; receive a first data burst from the first memory data signal interface, wherein a timing reference for the first data burst is provided by a DQS signal of a memory device coupled to the first memory data signal interface; delay the first data burst to align a phase difference between the DQS signal of the memory device and a clock signal of the interface circuit; and transmit the delayed first data burst to the memory controller; and initialization and configuration logic configured to; select the first memory data signal interface; issue a calibration read command, via the first memory data signal interface, to read test data stored at the first memory device; receive the test data from the first memory device across the first memory data signal interface; determine the phase difference between the DQS signal of the first memory device and the clock signal based on a timing of the received test data; and set a delay within the first memory data signal interface corresponding to the first memory device. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A computer-implemented method, comprising:
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selecting, by an interface circuit, a first memory data signal interface of a plurality of memory data signal interfaces; issuing, by the interface circuit, a calibration read command, via the first memory data signal interface, to read test data stored at a memory device coupled to the first memory data signal interface; receiving, by the interface circuit, the test data across the first memory data signal interface; determining, by the interface circuit, a phase difference between a first DQS signal and a clock signal based on a timing of the received test data; setting, by the interface circuit, a delay within the first memory data signal interface corresponding to the memory device coupled to the first memory data signal interface; receiving, by an interface circuit, a first read command from a memory controller; selecting, by the interface circuit, the first memory data signal interface of the plurality of memory data signal interfaces based on the first read command; receiving, by the interface circuit, a second read command from a memory controller; selecting, by the interface circuit, a second memory data signal interface of the plurality of memory data signal interfaces based on the second read command; receiving, by the interface circuit, a first data burst from the first memory data signal interface, wherein a timing reference for the first data burst is provided by the first DQS signal of the memory device coupled to the first memory data signal interface; receiving, by the interface circuit, a second data burst from the second memory data signal interface, wherein a timing reference for the second data burst is provided by a second, different, DQS signal of a memory device coupled to the second memory data signal interface; delaying, by the interface circuit, the first data burst to align the phase difference between the first DQS signal and the clock signal of the interface circuit; delaying, by the interface circuit, the second data burst to align a phase difference between the second DQS signal and the clock signal of the interface circuit; concatenating, by the interface circuit, the delayed first data burst and the delayed second data burst into a contiguous data burst; and transmitting, by the interface circuit, the contiguous data burst to the memory controller. - View Dependent Claims (14, 15, 16)
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Specification