Semiconductor process

• US 8,772,120 B2
• Filed: 05/24/2012
• Issued: 07/08/2014
• Est. Priority Date: 05/24/2012
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Hung, Yu-Hsiang, Liu, Chia-Jong, Wu, Yen-Liang, Chou, Pei-Yu, Chang, Chung-Fu, Huang, Shin-Chuan
• Primary Examiner(s): Matthews, Colleen
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US13/479,279
• Publication Number:
  US 20130316506A1
• Time in Patent Office: 775 Days
• Field of Search: 438/299, 438/300, 438/938, 438/301, 438/303, 257/E21.438
• US Class Current: 438/300
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A semiconductor process includes the following steps. A gate structure is formed on a substrate. A main spacer is formed on the substrate beside the gate structure. A source/drain is formed in the substrate beside the main spacer. After the source/drain is formed, an epitaxial structure is formed in the substrate beside the main spacer. A gate structure may be respectively formed in a first area and a second area of a substrate. A main spacer is formed on the substrate respectively beside the two gate structures. A source/drain is formed in the substrate respectively beside the two spacers. After the two source/drains are formed, an epitaxial structure is formed in the substrate respectively beside the main spacers.

Claims

1. A semiconductor process, comprising:

forming a gate structure on a substrate;

forming a main spacer on the substrate beside the gate structure;

forming a source/drain in the substrate beside the main spacer;

removing the main spacer;

forming an epitaxial spacer on the substrate beside the gate structure after the main spacer is removed;

forming a recess in the substrate beside the epitaxial spacer; and

performing an epitaxial process to form an epitaxial structure in the recess after the source/drain is formed.

2. The semiconductor process according to claim 1, wherein the steps of forming the source/drain comprise:

performing a source/drain ion implantation process to form the source/drain in the substrate beside the main spacer; and

performing a source/drain annealing process to activate the source/drain.

3. The semiconductor process according to claim 1, further comprising:

performing a stress memorization technique (SMT) to the substrate beneath the gate structure before the epitaxial structure is formed.

4. The semiconductor process according to claim 3, wherein the steps of performing the stress memorization technique (SMT) and forming the source/drain comprise:

performing a source/drain ion implantation process to form the source/drain in the substrate beside the main spacer;

forming a stress layer to cover the gate structure and the substrate; and

performing a source/drain annealing process to enable the stress layer to force stress to the substrate beneath the gate structure and to activate the source/drain.

5. The semiconductor process according to claim 4, further comprising:

removing the main spacer before the stress layer is formed, and etching the stress layer to form the epitaxial spacer before the epitaxial structure is formed.

6. The semiconductor process according to claim 1, wherein forming the epitaxial structure comprises performing an in-situ doping epitaxial process.

7. The semiconductor process according to claim 1, further comprising:

performing an ion implantation process in the epitaxial structure after the epitaxial structure is formed.

8. The semiconductor process according to claim 1, further comprising:

forming a first spacer on the substrate beside the gate structure before the main spacer is formed; and

forming a lightly doped source/drain in the substrate beside the first spacer.

9. The semiconductor process according to claim 1, wherein the epitaxial structure comprises a silicon phosphorus (SiP) epitaxial structure, a silicon germanium (SiGe) epitaxial structure or a carbon-containing silicon phosphorus (SiCP) epitaxial structure.

10. A semiconductor process, comprising:

forming a gate structure in a first area and a second area of a substrate respectively;

forming a main spacer on the substrate beside the two gate structures, respectively;

forming a source/drain in the substrate beside the two main spacers, respectively;

removing the two main spacers;

forming an epitaxial spacer on the substrate beside the two gate structures, respectively; and

self-aligning and forming two epitaxial structures in the substrate by the two epitaxial spacers beside the two gate structures, respectively, after the two source/drains are formed.

11. The semiconductor process according to claim 10, wherein the steps of forming the two source/drains comprise:

performing a source/drain ion implantation process to form the two source/drains; and

performing a source/drain annealing process to activate the two source/drains.

12. The semiconductor process according to claim 10, further comprising:

performing a stress memorization technique (SMT) to the substrate beneath the two gate structures before the two epitaxial structures are formed.

13. The semiconductor process according to claim 12, wherein the steps of performing the stress memorization technique (SMT) and forming the two source/drains comprise:

performing a source/drain ion implantation process to form the two source/drains in the substrate beside the two main spacers;

forming a stress layer to cover the two gate structures and the substrate;

performing a source/drain annealing process to enable the stress layer to force stresses to the substrate beneath the two gate structures and to activate the two source/drains.

14. The semiconductor process according to claim 13, further comprising:

removing the two main spacers before the stress layer is formed, and etching the stress layer to form the epitaxial spacer respectively before the two epitaxial structures are formed.

15. The semiconductor process according to claim 13, further comprising:

removing the two main spacers before the stress layer is formed, and etching the stress layer in the first area to form an epitaxial spacer in the first area before the two epitaxial structures are formed;

forming the epitaxial structure in the first area;

removing the remaining stress layer and the epitaxial spacer in the first area completely;

covering and patterning a material layer to enable the material layer to cover the first area and form an epitaxial spacer in the second area; and

forming the epitaxial structure in the second area.

16. The semiconductor process according to claim 10, wherein the two epitaxial structures all comprise a silicon phosphorus (SiP) epitaxial structure, a silicon germanium (SiGe) epitaxial structure or a carbon-containing silicon phosphorus (SiCP) epitaxial structure.

17. The semiconductor process according to claim 10, wherein forming the epitaxial structures comprises performing an in-situ doping epitaxial process.

18. The semiconductor process according to claim 10, further comprising:

forming a first spacer on the substrate beside the two gate structures respectively before the main spacers are formed; and

forming a lightly doped source/drain in the substrate beside the first spacers respectively.

19. The semiconductor process according to claim 10, further comprising:

performing an ion implantation process on at least one of the two epitaxial structures after the two epitaxial structures are formed.