Method and apparatus for minimizing skew between signals
First Claim
1. A signal delay measurement circuit, comprising:
- an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal, wherein the test clock signal is a clock input to the input register;
an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal, wherein the delayed version of the test clock signal is a clock input to the output register;
an emulation module connected between an output of the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the output of the input register to arrive at the output register as the delayed version of the test data signal; and
a delay chain defined to introduce a selectable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal.
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Abstract
Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.
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Citations
20 Claims
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1. A signal delay measurement circuit, comprising:
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an input register defined to receive a test data signal and output the test data signal in accordance with a test clock signal, wherein the test clock signal is a clock input to the input register; an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal, wherein the delayed version of the test clock signal is a clock input to the output register; an emulation module connected between an output of the input register and the output register, the emulation module defined to emulate an actual signal transmission path for which signal delay is to be measured, the emulation module defined to introduce signal delay in the test data signal as the test data signal is transmitted from the output of the input register to arrive at the output register as the delayed version of the test data signal; and a delay chain defined to introduce a selectable amount of signal delay in the test clock signal to generate the delayed version of the test clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A delay element calibration circuit, comprising:
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an input register defined to receive a test data signal and output the test data signal from an output of the input register in accordance with a test clock signal, wherein a period of the test clock signal is adjustable, and wherein the test clock signal is a clock input to the input register; an output register defined to receive a delayed version of the test data signal and output the delayed version of the test data signal in accordance with a delayed version of the test clock signal, wherein the delayed version of the test clock signal is a clock input to the output register; a first delay element connected between the output of the input register and an input of the output register, the first delay element defined to introduce signal delay in the test data signal as the test data signal is transmitted from the output of the input register to arrive at the input of the output register as the delayed version of the test data signal; and a chain of selectable second delay elements connected between the clock input to the input register and the clock input to the output register, wherein the chain of selectable second delay elements generates the delayed test clock signal, and wherein the delayed test clock signal has a selectable delay governed by the chain of selectable second delay elements. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A delay element calibration circuit, comprising:
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a first input register defined to receive a first test data signal and output the first test data signal in accordance with a first test clock signal; a first output register defined to receive a delayed version of the first test data signal and output the delayed version of the first test data signal in accordance with a delayed version of the first test clock signal; a first delay module, connected between the first input register and the first output register and defined to provide the delayed version of the first test data signal; a first delay chain defined to receive the first test clock signal and to provide the delayed version of the first test clock signal; a second input register defined to receive a second test data signal and to output the second test data signal in accordance with a second test clock signal; a second output register defined to receive a delayed version of the second test data signal and to output the delayed version of the second test data signal in accordance with the second test clock signal; and a second delay chain connected between the second input register and the second output register and defined to provide the delayed version of the second test data signal; wherein the second delay chain, the second input register and the second output register are configured to act as a calibration circuit for the first delay module or of the first delay chain. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification