Hardware task manager
First Claim
1. An integrated circuit comprising:
- a plurality of computing nodes, at least one of the plurality computing node comprising memory;
an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes to route data to at least one of the plurality of computing nodes; and
a hardware task manager in the at least one of the plurality of computing nodes, the hardware task manager configured to write input data to a local memory address based on parameters associated with an input port assigned to the data.
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Accused Products
Abstract
A hardware task manager for an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from tasks. Likewise, output buffers must also be available before the task can start to execute and store results. The hardware task manager maintains a counter associated with each buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and the buffer is not ready and the associated task cannot run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared indicating the input buffer has sufficient data and is available to be processed.
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Citations
20 Claims
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1. An integrated circuit comprising:
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a plurality of computing nodes, at least one of the plurality computing node comprising memory; an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes to route data to at least one of the plurality of computing nodes; and a hardware task manager in the at least one of the plurality of computing nodes, the hardware task manager configured to write input data to a local memory address based on parameters associated with an input port assigned to the data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for managing tasks within a computing device having a plurality of computing nodes, at least one computing node comprising a memory, an interconnection network operatively coupled to the plurality of computing nodes, the interconnection network configured to provide interconnections among the plurality of computing nodes to route data to at least one of the plurality of computing nodes, and a task manager in the at least one of the plurality of computing nodes, the method comprising:
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determining parameters associated with an input port assigned to data at the task manager; and writing the data to a local memory address based on the parameters. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification