Random delay generation for thin-film transistor based circuits
First Claim
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1. A circuit configured to generate a delay comprising:
- a) a delay element having an input terminal and an output terminal, the delay element comprising one or more inverters;
b) a capacitor having a first terminal receiving an input and a second terminal coupled to said input of said delay element; and
c) a thin-film field-effect transistor (TFT) having a first source/drain terminal receiving a DC source or supply voltage, a second source/drain terminal receiving said input of said delay element, and a gate electrically connected to said second source/drain terminal, said TFT being configured to provide a current and/or voltage to said capacitor,wherein said current and/or voltage has a value that falls randomly within a predetermined range.
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Abstract
Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.
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Citations
29 Claims
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1. A circuit configured to generate a delay comprising:
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a) a delay element having an input terminal and an output terminal, the delay element comprising one or more inverters; b) a capacitor having a first terminal receiving an input and a second terminal coupled to said input of said delay element; and c) a thin-film field-effect transistor (TFT) having a first source/drain terminal receiving a DC source or supply voltage, a second source/drain terminal receiving said input of said delay element, and a gate electrically connected to said second source/drain terminal, said TFT being configured to provide a current and/or voltage to said capacitor, wherein said current and/or voltage has a value that falls randomly within a predetermined range. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification