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Random delay generation for thin-film transistor based circuits

  • US 8,810,298 B2
  • Filed: 11/24/2009
  • Issued: 08/19/2014
  • Est. Priority Date: 11/26/2008
  • Status: Expired due to Fees
First Claim
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1. A circuit configured to generate a delay comprising:

  • a) a delay element having an input terminal and an output terminal, the delay element comprising one or more inverters;

    b) a capacitor having a first terminal receiving an input and a second terminal coupled to said input of said delay element; and

    c) a thin-film field-effect transistor (TFT) having a first source/drain terminal receiving a DC source or supply voltage, a second source/drain terminal receiving said input of said delay element, and a gate electrically connected to said second source/drain terminal, said TFT being configured to provide a current and/or voltage to said capacitor,wherein said current and/or voltage has a value that falls randomly within a predetermined range.

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