Nonvolatile semiconductor memory device and method for erasing data thereof
First Claim
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1. A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate;
a memory cell array comprising a memory string including a plurality of memory cells, the memory cells being stacked above the semiconductor substrate;
a plurality of word lines electrically connected to the plurality of memory cells;
a bit line electrically connected to one end of the memory string;
a source line electrically connected to the other end of the memory string;
a drain-side select transistor electrically connected to both one end of the memory string and the bit line;
a source-side select transistor electrically connected to both the other end of the memory string and the source line; and
a control circuit configured to perform an erase operation, the erase operation including a first phase and a second phase performed after the first phase,the control circuit being configured to perform the erase operation on the condition that a first voltage is applied to at least one of a gate of the drain-side select transistor and a gate of the source-side select transistor in a selected memory string during the first phase and the second phase, a second voltage is applied to a first word line during the second phase, and a third voltage is applied to a second word line during the second phase, the first word line being electrically connected to a gate of a first memory cell in the selected memory string, the second word line being electrically connected to a gate of a second memory cell in the selected memory string, and the third voltage being smaller than the second voltage.
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Abstract
A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.
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Citations
18 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate; a memory cell array comprising a memory string including a plurality of memory cells, the memory cells being stacked above the semiconductor substrate; a plurality of word lines electrically connected to the plurality of memory cells; a bit line electrically connected to one end of the memory string; a source line electrically connected to the other end of the memory string; a drain-side select transistor electrically connected to both one end of the memory string and the bit line; a source-side select transistor electrically connected to both the other end of the memory string and the source line; and a control circuit configured to perform an erase operation, the erase operation including a first phase and a second phase performed after the first phase, the control circuit being configured to perform the erase operation on the condition that a first voltage is applied to at least one of a gate of the drain-side select transistor and a gate of the source-side select transistor in a selected memory string during the first phase and the second phase, a second voltage is applied to a first word line during the second phase, and a third voltage is applied to a second word line during the second phase, the first word line being electrically connected to a gate of a first memory cell in the selected memory string, the second word line being electrically connected to a gate of a second memory cell in the selected memory string, and the third voltage being smaller than the second voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for erasing data of a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including:
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a semiconductor substrate; a memory cell array comprising a memory string comprising a plurality of memory cells, the memory cells being stacked above the semiconductor substrate; a plurality of word lines electrically connected to the plurality of memory cells; a bit line electrically connected to one end of the memory string; a source line electrically connected to the other end of the memory string; a drain-side select transistor electrically connected to both one end of the memory string and the bit line; and a source-side select transistor electrically connected to both the other end of the memory string and the source line, the method comprising performing an erase operation, the erase operation including a first phase and a second phase performed after the first phase, applying a first voltage to at least one of a gate of the drain-side select transistor and a gate of the source-side select transistor in a selected memory string during the first phase and the second phase, applying a second voltage to a first word line during the second phase, and applying a third voltage to a second word line during the second phase, the first word line being electrically connected to a gate of a first memory cell in the selected memory string, the second word line being electrically connected to a gate of a second memory cell in the selected memory string, and the third voltage being smaller than the second voltage. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification