Nonvolatile semiconductor memory device and method for erasing data thereof

• US 8,817,538 B2
• Filed: 06/11/2012
• Issued: 08/26/2014
• Est. Priority Date: 06/14/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Itagaki, Kiyotaro, Iwata, Yoshihisa, Yamada, Kunihiro
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US13/493,370
• Publication Number:
  US 20120320698A1
• Time in Patent Office: 806 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.18, 365/185.23, 365/185.27, 365/185.28, 365/185.29, 365/185.33
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

a memory cell array comprising a memory string including a plurality of memory cells, the memory cells being stacked above the semiconductor substrate;

a plurality of word lines electrically connected to the plurality of memory cells;

a bit line electrically connected to one end of the memory string;

a source line electrically connected to the other end of the memory string;

a drain-side select transistor electrically connected to both one end of the memory string and the bit line;

a source-side select transistor electrically connected to both the other end of the memory string and the source line; and

a control circuit configured to perform an erase operation, the erase operation including a first phase and a second phase performed after the first phase,

the control circuit being configured to perform the erase operation on the condition that a first voltage is applied to at least one of a gate of the drain-side select transistor and a gate of the source-side select transistor in a selected memory string during the first phase and the second phase, a second voltage is applied to a first word line during the second phase, and a third voltage is applied to a second word line during the second phase, the first word line being electrically connected to a gate of a first memory cell in the selected memory string, the second word line being electrically connected to a gate of a second memory cell in the selected memory string, and the third voltage being smaller than the second voltage.

2. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a drain-side select gate line electrically connected to the gate of the drain-side select transistor; and

a source-side select gate line electrically connected to the gate of the source-side select transistor,

wherein,

in a first non-selected memory string electrically connected to the bit line and the source line in common with the selected memory string, the control circuit is configured to apply a fourth voltage to at least one of the drain-side select gate line and the source-side select gate line.

3. The nonvolatile semiconductor memory device according to claim 2, wherein the control circuit is configured to apply a fifth voltage to the bit line and the source line, and

wherein the fifth voltage is set to a value that prevents data held in a memory cell from being changed when the fifth voltage is applied to the semiconductor layer, and the second voltage is applied to the first word line.

4. The nonvolatile semiconductor memory device according to claim 2, wherein the control circuit is configured to apply a fifth voltage to the bit line and the source line, and

wherein the fifth voltage is set to a value that prevents data held in a memory cell from being changed when the fifth voltage is applied to the semiconductor layer, and the third voltage is applied to the second word line.

5. The nonvolatile semiconductor memory device according to claim 3, wherein the fifth voltage is set to a value that prevents data held in a memory cell from being changed when the fifth voltage is applied to the semiconductor layer, and when the third voltage is applied to the second word line.

6. The nonvolatile semiconductor memory device according to claim 1, wherein the erase operation comprises a soft-erase operation, the soft-erase operation being performed after a writing operation.

7. The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit raises a voltage of the first word line to the second voltage in several stages.

8. The nonvolatile semiconductor memory device according to claim 2, wherein the second voltage and the fourth voltage are positive voltages, the third voltage is negative voltage, and the first voltage is ground voltage.

9. The nonvolatile semiconductor memory device according to claim 2, wherein the second voltage, the first voltage, and the fourth voltage are positive voltages, and the third voltage is a ground voltage.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell comprises:

a first semiconductor layer;

a charge accumulation layer surrounding the first semiconductor layer; and

a first conductive layer surrounding the charge accumulation layer.

11. The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit is configured to set the drain-side select transistor and the source-side select transistor in the selected memory string to non-conductive states by applying the first voltage.

12. A method for erasing data of a nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device including:

a semiconductor substrate;

a memory cell array comprising a memory string comprising a plurality of memory cells, the memory cells being stacked above the semiconductor substrate;

a plurality of word lines electrically connected to the plurality of memory cells;

a bit line electrically connected to one end of the memory string;

a source line electrically connected to the other end of the memory string;

a drain-side select transistor electrically connected to both one end of the memory string and the bit line; and

a source-side select transistor electrically connected to both the other end of the memory string and the source line,

the method comprising performing an erase operation, the erase operation including a first phase and a second phase performed after the first phase, applying a first voltage to at least one of a gate of the drain-side select transistor and a gate of the source-side select transistor in a selected memory string during the first phase and the second phase, applying a second voltage to a first word line during the second phase, and applying a third voltage to a second word line during the second phase, the first word line being electrically connected to a gate of a first memory cell in the selected memory string, the second word line being electrically connected to a gate of a second memory cell in the selected memory string, and the third voltage being smaller than the second voltage.

13. The method for erasing data of a nonvolatile semiconductor memory device according to claim 12, the nonvolatile semiconductor memory device further including:

a drain-side select gate line electrically connected to the gate of the drain-side select transistor; and

a source-side select gate line electrically connected to the gate of the source-side select transistor,

wherein,

in a first non-selected memory string electrically connected to the bit line and the source line in common with the selected memory string, the method applies a fourth voltage to at least one of the drain-side select gate line and the source-side select gate line.

14. The method for erasing data of a nonvolatile semiconductor memory device according to claim 13, wherein the method applies a fifth voltage to the bit line and the source line, and

wherein the fifth voltage is set to a value that prevents data held in a memory cell from being changed when the fifth voltage is applied to the semiconductor layer, and the second voltage is applied to the first word line.

15. The method for erasing data of a nonvolatile semiconductor memory device according to claim 13, wherein the method applies a fifth voltage to the bit line and the source line, and

wherein the fifth voltage is set to a value that prevents data held in a memory cell from being changed when the fifth voltage is applied to the semiconductor layer, and the third voltage is applied to the second word line.

16. The method for erasing data of a nonvolatile semiconductor memory device according to claim 14, wherein the fifth voltage is set to a value that prevents data held in a memory cell from being changed when the fifth voltage is applied to the semiconductor layer, and the third voltage is applied to the second word line.

17. The method for erasing data of a nonvolatile semiconductor memory device according to claim 12, wherein the erase operation includes a soft-erase operation, the soft-erase operation being performed after a writing operation.

18. The method for erasing data of a nonvolatile semiconductor memory device according to claim 12, wherein a voltage of the first word line is raised to the second voltage in several stages.