Process for preparing a bonding type semiconductor substrate

• US 8,829,488 B2
• Filed: 08/27/2012
• Issued: 09/09/2014
• Est. Priority Date: 06/09/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Furukawa, Kazuyoshi, Akaike, Yasuhiko, Yoshitake, Shunji
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Yushina, Galina
• Application Number:
  US13/595,284
• Publication Number:
  US 20130020681A1
• Time in Patent Office: 743 Days
• Field of Search: 257/12, 257/13, 257/76, 257/78, 257/79, 257/84, 257/85, 257/94, 257/96, 257/99, 257/103, 257/183, 257/190, 257/196, 257/414, 257/431, 257/E33.001, 257/E33.023, 257/E33.026, 257/E33.031, 257/E33.027, 257/E33.032, 257/E33.045, 257/E27.137, 257/E23.023, 257/E21.088, 257/E21.148
• US Class Current: 257/13
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/10 with a light reflecting structure, e.g. semiconductor Bragg reflector
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate

Abstract

Provided is a laminate containing a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×10¹⁸ cm³ or more.

Claims

1. A laminate comprising:

a first compound semiconductor layer; and

a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer,

wherein a surface where a (111) A plane preferentially appears in the second compound semiconductor layer is bonded to a surface where a (111) B plane preferentially appears in the first compound semiconductor layer, or a surface where a (111) B plane preferentially appears in the second compound semiconductor layer is bonded to a surface where a (111) A plane preferentially appears in the first compound semiconductor layer, and

an impurity concentration of the bonding layer is 2×

10¹⁸ cm³ or more.

2. The laminate according to claim 1, wherein the bonding layer comprises a bonding material.

3. The laminate according to claim 1, wherein a surface where a (111) A plane preferentially appears in the second compound semiconductor layer is bonded to a surface where a (111) B plane preferentially appears in the first compound semiconductor layer.

4. The laminate according to claim 1, wherein a surface where a (111) B plane preferentially appears in the second compound semiconductor layer is bonded to a surface where a (111) A plane preferentially appears in the first compound semiconductor layer.

5. The laminate according to claim 1, wherein the bonding layer comprises an epitaxial growth layer.

6. The laminate according to claim 5, wherein the epitaxial growth layer comprises a InGaAlP layer or a GaP layer.

7. A laminate comprising:

a first compound semiconductor layer; and

a second compound semiconductor layer,

wherein

both the first and second compound semiconductor layers have a top side surface inclined to the (111) group III face and a back side surface inclined to the (111) group V face,

the top side surface of the first semiconductor layer is integrally bonded via a bonding layer to the back side surface of the second compound semiconductor layer, and

an impurity concentration of the bonding layer is 2×

10¹⁸ cm<sup>−

3</sup> or more.