Semiconductor device and manufacturing method thereof

• US 8,921,948 B2
• Filed: 01/09/2012
• Issued: 12/30/2014
• Est. Priority Date: 01/12/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US13/345,795
• Publication Number:
  US 20120175608A1
• Time in Patent Office: 1,086 Days
• Field of Search: 257/57, 257/64, 257/65, 257/66, 257/213, 257/288, 257/327, 257/387, 257/401, 257/E29.021, 257/E29.039, 257/E29.116, 257/E29.119, 257/E29.12, 257/E29.122, 257/E29.268
• US Class Current: 257/401
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 21/469 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After-treatment of these layers
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched.

Claims

1. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer; and

a source electrode and a drain electrode over the oxide semiconductor layer,

wherein an entire bottom surface of the source electrode and an entire bottom surface of the drain electrode are in contact with the oxide semiconductor layer,

wherein an outer edge of a first part of the oxide semiconductor layer coincides with part of an outer edge of the source electrode,

wherein an outer edge of a second part of the oxide semiconductor layer coincides with part of an outer edge of the drain electrode,

wherein the first part and the second part of the oxide semiconductor layer intersect with an outer edge of the gate electrode, and

wherein a third part of the oxide semiconductor layer which is provided inside the outer edge of the gate electrode has a width larger than a width of each of the first part, the second part, the source electrode and the drain electrode.

2. The semiconductor device according to claim 1, wherein a total length of parts of an outer edge of the oxide semiconductor layer which does not overlap with the source electrode and the drain electrode is more than five times as long as a channel length of the semiconductor device.

3. The semiconductor device according to claim 1, further comprising an insulating film containing oxygen over the oxide semiconductor layer, the source electrode and the drain electrode, wherein the insulating film covers a side surface of the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, and Zn.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is non-single-crystal.

6. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer;

a source electrode and a drain electrode over the oxide semiconductor layer; and

an insulating film containing oxygen over the oxide semiconductor layer, the source electrode and the drain electrode,

wherein the insulating film covers a side surface of the oxide semiconductor layer,

wherein an entire bottom surface of the source electrode and an entire bottom surface of the drain electrode overlap with the oxide semiconductor layer,

wherein an outer edge of a first part of the oxide semiconductor layer coincides with part of an outer edge of the source electrode,

wherein an outer edge of a second part of the oxide semiconductor layer coincides with part of an outer edge of the drain electrode,

wherein each of the first part and the second part of the oxide semiconductor layer intersects with an outer edge of the gate electrode, and

wherein a third part of the oxide semiconductor layer which is provided inside the outer edge of the gate electrode has a width lamer than a width of each of the first part, the second part, the source electrode and the drain electrode.

7. The semiconductor device according to claim 6, further comprising:

a source region between the entire bottom surface of the source electrode and the oxide semiconductor layer; and

a drain region between the entire bottom surface of the drain electrode and the oxide semiconductor layer,

wherein each of the source region and the drain region comprises a conductive metal oxide layer.

8. The semiconductor device according to claim 6, further comprising an insulating layer over and in contact with the oxide semiconductor layer,

wherein the source electrode and the drain electrode are over and in contact with the insulating layer.

9. The semiconductor device according to claim 6, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, and Zn.

10. The semiconductor device according to claim 6, wherein the oxide semiconductor layer is non-single-crystal.