Three dimensional structure memory
DC CAFCFirst Claim
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1. An apparatus comprising:
- a first integrated circuit having a thickness Th1;
a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th2; and
hundreds of vertical interconnect segments interconnecting the first and second integrated circuits including a plurality of vertical interconnect segments having lengths of Th1+Th2 or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits;
wherein at least one of the first integrated circuit and the second integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed surface.
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Abstract
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
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Citations
95 Claims
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1. An apparatus comprising:
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a first integrated circuit having a thickness Th1; a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th2; and hundreds of vertical interconnect segments interconnecting the first and second integrated circuits including a plurality of vertical interconnect segments having lengths of Th1+Th2 or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits; wherein at least one of the first integrated circuit and the second integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed surface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57)
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58. An apparatus comprising:
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a first integrated circuit layer having a thickness Th1; a second integrated circuit layer in a stacked relationship with and adjacent to the first integrated circuit layer having a thickness Th2; and a plurality of vertical interconnect segments interconnecting the first and second integrated circuit layers, wherein each vertical interconnect segment forms an interconnection only between a pair of adjacent integrated circuits; wherein the vertical interconnect segments have lengths of Th1+Th2 or less; and wherein at least one of the first integrated circuit and the second integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed surface. - View Dependent Claims (59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89)
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90. An apparatus comprising:
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a first integrated circuit having a thickness Th1; a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th2; and hundreds of vertical interconnect segments interconnecting the first and second integrated circuits including a plurality of vertical interconnect segments having lengths of Th1+Th2 or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits; and a low-stress silicon-based dielectric layer having a tensile stress of less than 5×
108 dynes/cm2;
wherein;a process technology used to make the first integrated circuit is different from a process technology used to make the second integrated circuit; the first integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed backside surface; the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; the first integrated circuit has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges; and
,the second integrated circuit comprises an array of memory cells formed with at least one silicon-based dielectric layer having a tensile stress of less than 5×
108 dynes/cm2 and without a monocrystalline semiconductor substrate. - View Dependent Claims (91)
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92. An apparatus comprising:
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a first integrated circuit having a thickness Th1; a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th2; and hundreds of vertical interconnect segments interconnecting the first and second integrated circuit including a plurality of vertical interconnect segments having lengths of Th1+Th2 or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits; and a low-stress silicon-based dielectric layer having a tensile stress of less than 5×
108 dynes/cm2;
wherein;a process technology used to make the first integrated circuit is different from a process technology used to make the second integrated circuit; the first integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed backside surface; the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; the first integrated circuit has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges; the second integrated circuit comprising an array of non-volatile memory cells formed with at least one silicon-based dielectric layer having a tensile stress of less than 5×
108 dynes/cm2; and
,the first integrated circuit of the plurality of substantially flexible integrated circuits comprising circuitry for storing a plurality of data bits per memory cell. - View Dependent Claims (93)
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94. An apparatus comprising:
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a first integrated circuit having a thickness Th1; a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th2; and hundreds of vertical interconnect segments interconnecting the first and second integrated circuits including a plurality of vertical interconnect segments having lengths of Th1+Th2 or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits; and one or more low-stress silicon-based dielectric layer having a tensile stress of less than 5×
108 dynes/cm2;
wherein;a process technology used to make the first integrated circuit is different from a process technology used to make the second integrated circuit; the first integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed backside surface; the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; the first integrated circuit has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges; the apparatus is substantially flexible based on a combination of low stress of the one or more low-stress dielectric layers and the monocrystalline semiconductor substrate being substantially flexible; the second integrated circuit comprising an array of non-volatile memory cells formed with at least one silicon-based dielectric layer having a tensile stress of less than 5×
108 dynes/cm2;the first integrated circuit comprising circuitry for storing a plurality of data bits per memory cell; and
,the first integrated circuit comprising error correction circuitry for detecting and correcting data read errors from the non-volatile memory cells of the second integrated circuit. - View Dependent Claims (95)
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Specification