Method and apparatus for vector execution on a scalar machine

• US 8,935,515 B2
• Filed: 08/20/2009
• Issued: 01/13/2015
• Est. Priority Date: 12/15/2004
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Colavin, Osvaldo M., Rizzo, Davide, Soni, Vineet, Schubert, William L. Jr.
• Primary Examiner(s): Caldwell, Andrew
• Assistant Examiner(s): LINDLOF, JOHN M
• Application Number:
  US12/544,250
• Publication Number:
  US 20090313458A1
• Time in Patent Office: 1,972 Days
• Field of Search: None
• US Class Current: 712/229
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/345 of multiple operands or results addressing multiple banks G06F12/06
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

Claims

1. A processor comprising:

a) an instruction decode circuit having an address output, the instruction decode circuit being configured to determine an address specified by an instruction and to provide the specified address at the address output of the instruction decode circuit;

b) a rename circuit having

     1) an address input coupled to the address output of the instruction decode circuit, and

     2) an address output, the rename circuit comprising;

i) a counter configured to count a number of times the instruction decode circuit has consecutively decoded the instruction;

ii) an arithmetic circuit having

     1) a first input coupled to the address input of the rename circuit,

     2) a second input coupled to the counter, and

     3) a renamed output, wherein the arithmetic circuit is configured to provide at the renamed output a renamed value representing;

the specified address received from the address output of the instruction decode circuit via the address input of the rename circuit,

added to a value stored in a first register, the value being indicative of a number of vector iterations that have been completed prior to a current vector run, and

offset by an amount that is based on a number of times the processor, while operating in a vector mode, has executed the instruction during the current vector run;

iii) a switching circuit having

     1) a first input coupled to the address input of the rename circuit,

     2) a second input coupled to the renamed output of the arithmetic circuit,

     3) a control input, and

     4) an output coupled to the address output of the rename circuit, wherein the switching circuit is configured to selectively couple a value at the first input of the switching circuit or the renamed value at the second input of the switching circuit to the output of the switching circuit based on a value of the control input; and

c) a data access circuit having an address input coupled to the address output of the rename circuit.

2. The processor of claim 1, additionally comprising a plurality of output lines and instruction execution circuitry, the instruction execution circuitry controlling values on the plurality of output lines.

3. A portable electronic device comprising:

a) a processor according to claim 2;

b) a user interface having a data input coupled to the output lines of the processor.

4. The processor of claim 1, additionally comprising a register file having a plurality of storage locations each having an address associated therewith, wherein the data access circuit is configured to access a storage location in the register file at an address specified by a value at the address input of the data access circuit.

5. The processor of claim 4, wherein the register file comprises a predetermined number of locations and the arithmetic circuit is configured to provide the renamed value using modular arithmetic with a modulus less than the predetermined number of locations in the register file.

6. The processor of claim 5, additionally comprising an upper bound register storing a value representative of an address in the register file, wherein the arithmetic circuit is configured to provide the renamed value using modular arithmetic with a modulus equal to the value in the upper bound register.

7. The processor of claim 6, wherein the rename circuit additionally comprises control logic having 1) a first input coupled to the upper bound register, 2) a second input coupled to the address input of the rename circuit, and 3) an output coupled to the control input of the switching circuit.

8. The processor of claim 7, wherein the control logic is adapted to set a value on the output of the control logic in response to a relation between a value at the first input of the control logic and a value at the second input of the control logic.

9. The processor of claim 6, wherein:

a) the rename circuit additionally comprises a second counter and a vector length register holding a value, wherein the second counter is adapted to count in increments determined by the value in the vector length register;

b) the arithmetic circuit has a third input coupled to the second counter; and

c) the amount by which the specified address received at the first input of the arithmetic circuit is offset is proportional to the value at the second input of the arithmetic circuit and the value to which the specified address is added is based on a value at the third input of the arithmetic circuit.

10. The processor of claim 1, wherein the processor comprises at least a first pipeline stage and a second pipeline stage, wherein the decode circuit is within the first pipeline stage and the rename circuit is within the second pipeline stage.

14. The processor of claim 1, wherein:

the rename circuit is configured to update the value stored in the first register at a start of execution of each vector iteration in at least one loop.

15. The processor of claim 14, wherein:

the rename circuit is configured to, at a start of execution of a vector iteration other than a first vector iteration of the at least one loop, update the value stored in the first register based on a vector length.

16. The processor of claim 1, wherein the instruction is a first instruction, and wherein at least one of the vector iterations that have been completed prior to the current vector run comprises:

a prior vector run of the first instruction, and

an execution of a second instruction different from the first instruction.

11. A processor configured to execute a first instruction a consecutive plurality of times, the processor comprising:

a) instruction decode circuitry configured to determine an address specified by the first instruction;

b) rename circuitry configured to rename the specified address received from the instruction decode circuitry, wherein the rename circuitry is configured to rename the specified address based on;

a number of times the processor, while operating in a vector mode, has executed the first instruction during a current vector run, and

a number of vector iterations that have been completed prior to the current vector run;

c) instruction execute circuitry configured to execute the first instruction; and

d) write circuitry configured to write a result of executing the first instruction to the renamed address.

12. The processor of claim 11, further comprising fetch circuitry configured to stall fetching of a second instruction until after the first instruction has been issued the consecutive plurality of times.

13. The processor of claim 11, wherein the write circuitry is configured to write the result to a rotating register file.