Asymmetric semiconductor memory device having electrically floating body transistor

• US 8,957,458 B2
• Filed: 09/26/2011
• Issued: 02/17/2015
• Est. Priority Date: 03/24/2011
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): NGUYEN, DUY T V
• Application Number:
  US13/244,899
• Publication Number:
  US 20120217549A1
• Time in Patent Office: 1,240 Days
• Field of Search: 257/204, 257/348, 257/E27.07
• US Class Current: 257/204
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7308 Schottky transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Claims

1. An asymmetric bi-stable semiconductor memory cell comprising:

a floating body region having at least two stable charge levels indicative of a state of the asymmetric bi-stable semiconductor memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a third region in direct electrical contact with said floating body region and located below said floating body region; and

a gate positioned between said first and second regions, such that said first region is on a first side of said memory cell relative to said gate and said second region is on a second side of said memory cell relative to said gate wherein said gate is spaced apart from said first region;

wherein performance characteristics of said first side are different from performance characteristics of said second side.

2. The asymmetric bi-stable semiconductor memory cell of claim 1, further comprising a gap region on a surface of said floating body region, said gap region located between said first region and said gate.

3. The asymmetric bi-stable semiconductor memory cell of claim 1, further comprising:

a substrate; and

wherein said third region comprises a buried layer in said substrate, wherein said substrate is separated from said floating body region by said buried layer.

4. The asymmetric semiconductor memory cell of claim 3, further comprising:

a word line terminal electrically connected to said gate;

a bit line terminal electrically connected to said first region;

a source line terminal electrically connected to said second region;

a buried well terminal electrically connected to said buried layer; and

a substrate terminal electrically connected to said substrate.

5. The asymmetric semiconductor memory cell of claim 1, further comprising an insulating layer insulating said gate from said floating body region.

6. The asymmetric semiconductor memory cell of claim 1, wherein said second region is electrically connected to a gate of a switching transistor to configure connectivity of gates in a field programmable logic array (FPGA).

7. The asymmetric semiconductor memory cell of claim 1 configured to function as a configuration memory, wherein said second region is electrically connected to a gate of a switching transistor that is connected to interconnect lines connected to a field programmable logic array (FPGA);

and

an inverter and a p-channel metal-oxide-semiconductor (PMOS) transistor are connected to one of said interconnect lines to restore values of signals passed between said interconnect lines.

8. The asymmetric bi-stable semiconductor memory cell of claim 1, further comprising

a silicon-on-insulator substrate;

and

a buried insulator layer, wherein said buried insulator layer insulates said silicon-on-insulator substrate from said floating body region.

9. The asymmetric bi-stable semiconductor memory cell of claim 1, wherein

said floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first region has a second conductivity type selected from said p-type conductivity type and said n-type conductivity type, said second conductivity type being different from said first conductivity type; and

said second region has said second conductivity type.

10. The semiconductor memory cell of claim 1, arranged in an array of said semiconductor memory cells comprising at least one row of said cells and a plurality of columns of said cells or at least one column of said cells and a plurality of rows of said cells.

11. An asymmetric semiconductor memory cell comprising:

a single floating body region comprising means for storing a charge or lack of charge indicative of a state of the asymmetric semiconductor memory cell;

a first region in electrical contact with said single floating body region;

an electrode electrically connected to said single floating body region, wherein said electrode forms a Schottky contact with said single floating body region;

a gate positioned between said first region and said electrode; and

a second region in electrical contact with said first region, where said second region has a different conductivity type from said first region, wherein said second region is spaced a part from said gate.

12. The asymmetric semiconductor memory cell of claim 11, further comprising:

a substrate; and

a buried layer in said substrate having a different conductivity type from said substrate, wherein said substrate is separated from said floating body region by said buried layer.

13. The asymmetric semiconductor memory cell of claim 11, further comprising:

a silicon-on-insulator substrate; and

a buried insulator layer, wherein said buried insulator layer insulates said silicon-on-insulator substrate from said floating body region.

14. The asymmetric semiconductor memory cell of claim 11, wherein said first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

and

said floating body region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.

15. The asymmetric semiconductor memory cell of claim 11, further comprising an insulating layer insulating said gate from said floating body region.

16. The asymmetric semiconductor memory cell of claim 15, wherein said floating body region underlies and contacts said insulating layer under an entirety of said gate.

17. The asymmetric semiconductor memory cell of claim 11, further comprising a gap region on a surface of said floating body region, said gap region located between said electrode and said gate.

18. The asymmetric semiconductor memory cell of claim 11, arranged in an array of said semiconductor memory cells comprising at least one row of said cells and a plurality of columns of said cells or at least one column of said cells and a plurality of rows of said cells.

19. The asymmetric semiconductor memory cell of claim 11, further comprising means for sensing a state of said memory cell.

20. An asymmetric semiconductor memory cell comprising:

a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;

said floating body region comprising means for storing a charge or lack of charge indicative of a state of the asymmetric semiconductor memory cell;

a first region having said first conductivity type and being in direct contact with said floating body region;

a gate positioned above said floating body region; and

a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type, said second conductivity type being different from said first conductivity type, wherein said gate is spaced apart from said first region.

21. The asymmetric semiconductor memory cell of claim 20, further comprising:

a substrate; and

a buried layer in said substrate, wherein said substrate is separated from said floating body region by said buried layer.

22. The asymmetric semiconductor memory cell of claim 20, further comprising:

a silicon-on-insulator substrate; and

a buried insulator layer, wherein said buried insulator layer insulates said silicon-on-insulator substrate from said floating body region.

23. The asymmetric semiconductor memory cell of claim 20, wherein said first region is electrically connected to a gate of a switching transistor to configure connectivity of gates in a field programmable logic array (FPGA).

24. The asymmetric semiconductor memory cell of claim 20, wherein said memory cell is useable as a reference cell by applying an intermediate potential between a first potential indicative of a logic-0 state and second potential indicative of a logic-1 state to said floating body region through a second region.

25. The asymmetric semiconductor memory cell of claim 20, configured for use as a reference cell, further comprising a third region in electrical contact with said floating body region, said third region having said second conductivity type.

26. The asymmetric semiconductor memory cell of claim 25, wherein said third region is located between said gate and said first region.

27. The asymmetric semiconductor memory cell of claim 20, arranged in an array of said semiconductor memory cells comprising at least one row of said cells and a plurality of columns of said cells or at least one column of said cells and a plurality of rows of said cells.

28. The asymmetric semiconductor memory cell of claim 20 configured to function as a configuration memory, wherein said first region is electrically connected to a gate of a switching transistor that is connected to interconnect lines connected to a field programmable logic array (FPGA);

and

an inverter and a p-channel metal-oxide-semiconductor (PMOS) transistor are connected to one of said interconnect lines to restore values of signals passed between said interconnect lines.

29. A memory array comprising:

a plurality of asymmetric, bi-stable semiconductor memory cells, each said asymmetric, bi-stable memory cell comprising;

a single floating body region having at least two stable charge levels indicative of a state of the memory cell;

a first region in direct contact with said single floating body region;

a second region in direct contact with said single floating body region and spaced apart from said first region; and

a gate positioned between said first and second regions, such that said first region is on a first side of said memory cell relative to said gate and said second region is on a second side of said memory cell relative to said gate, wherein performance characteristics of said first side are different from performance characteristics of said second side, wherein said gate is spaced apart from said first region;

a substrate; and

a buried layer in said substrate, wherein said substrate is separated from said single floating body region by said buried layer;

at least two of said memory cells being commonly connected to at least one of;

a word line terminal electrically connected to said gates, respectively, of said at least two memory cells;

a bit line terminal electrically connected to said first regions, respectively, of said at least two memory cells;

a source line terminal electrically connected to said second regions, respectively, of said at least two memory cells;

a buried well terminal electrically connected to said buried layers, respectively, of said at least two memory cells;

or

a substrate terminal electrically connected to said substrates, respectively, of said at least two memory cells.

30. The memory array of claim 29, wherein said plurality of asymmetric, bi-stable semiconductor memory cells are arranged in an at least one row of said cells and a plurality of columns of said cells or at least one column of said cells and a plurality of rows of said cells.