Dense arrays and charge storage devices

• US 8,981,457 B2
• Filed: 05/10/2012
• Issued: 03/17/2015
• Est. Priority Date: 08/14/2000
• Status: Expired due to Fees

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Lee, Thomas H., Subramanian, Vivek, Cleeves, James M., Johnson, Mark G., Farmwald, Paul Michael, Kouznetzov, Igor G.
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US13/468,731
• Publication Number:
  US 20120223380A1
• Time in Patent Office: 1,041 Days
• Field of Search: 257/321, 257/329, 257/324, 257/E29.262, 257/E29.309, 257/E29.304
• US Class Current: 257/321
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/8616 : Charge trapping diodes
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 : with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Claims

1. A memory device, comprising:

a substrate;

a first contact located over the substrate;

a first vertical semiconductor pillar located over the first contact, a first end of the first vertical semiconductor pillar contacting the first contact;

a second contact located over the first vertical semiconductor pillar, wherein a second end of the first vertical semiconductor pillar contacts the second contact;

a second vertical semiconductor pillar located horizontally adjacent to the first vertical semiconductor pillar in a first row over the substrate;

a third vertical semiconductor pillar located horizontally adjacent to the first vertical semiconductor pillar in a second row different from the first row over the substrate;

third contacts coupling to the second vertical semiconductor pillar;

fourth contacts coupling to the third vertical semiconductor pillar;

a first charge storage region located adjacent to a first portion of a first side of the first vertical semiconductor pillar;

a second charge storage region located adjacent to a second portion of the first vertical semiconductor pillar above the first portion of the first vertical semiconductor pillar, wherein the first and second charge storage regions are two portions of a single contiguous material layer vertically extending from the first end of the first vertical semiconductor pillar to the second end of the first vertical semiconductor pillar;

a first control gate located adjacent to the first charge storage region;

a second control gate located adjacent to the second charge storage region;

a first tunneling dielectric layer located between the first side of the first vertical semiconductor pillar and the first charge storage region, between a bottom of the first charge storage region and the first contact, and between the first contact and the first control gate;

a first blocking dielectric layer located between the first charge storage region and the first control gate, and between the first contact and the first control gate; and

driver circuitry associated with the operation of the memory device;

wherein the first control gate is located entirely above the first contact;

wherein the first vertical semiconductor pillar comprises a first conductivity type semiconductor region in the first end, another first conductivity type region in the second end, and a second conductivity type region between the first conductivity type regions;

wherein the first conductivity type regions comprise n-type regions and the second conductivity type region comprises a p-type region; and

wherein the first control gate is shared between the first vertical semiconductor pillar, the second vertical semiconductor pillar and the third vertical semiconductor pillar.

2. The memory device of claim 1, wherein the first conductivity type regions comprise source and drain regions and the second conductivity type region comprises a channel region.

3. The memory device of claim 1, wherein the device comprises a three dimensional memory device, the first control gate is located adjacent to the first charge storage region in a first level, and the second control gate is located adjacent to the second charge storage region in a second level above the first level.

4. The memory device of claim 1, wherein the first control gate is located between the first vertical semiconductor pillar, the second vertical semiconductor pillar and the third vertical semiconductor pillar.

5. The memory device of claim 4, wherein:

the memory device further comprises a plurality of horizontally separated vertical semiconductor pillars;

the first control gate is shared between the plurality of horizontally separated vertical semiconductor pillars; and

the first control gate is located between the plurality of horizontally separated vertical semiconductor pillars.

6. The memory device of claim 5, wherein:

the plurality of horizontally separated vertical semiconductor pillars comprise a three by three array of horizontally separated vertical semiconductor pillars;

the first control gate is shared among the three by three array of horizontally separated vertical semiconductor pillars; and

the first control gate is located among the horizontally separated vertical semiconductor pillars of the three by three array of horizontally separated vertical semiconductor pillars.

7. The memory device of claim 5, wherein the plurality of horizontally separated vertical semiconductor pillars each have a substantially circular shape when viewed from above.

8. The memory device of claim 1, wherein the first vertical semiconductor pillar comprises substantially vertical sidewalls that extend from the first end of the first vertical semiconductor pillar to the second end of the first vertical semiconductor pillar, and the first vertical semiconductor pillar further comprises an additional first conductivity type semiconductor region located between the first conductivity type semiconductor region and said another first conductivity type semiconductor region, and all sidewalls of the additional first conductivity type semiconductor region are within the substantially vertical sidewalls of the first vertical semiconductor pillar.

9. A memory device, comprising:

a substrate;

a first contact located over the substrate;

a first vertical semiconductor pillar located over the first contact, a first end of the first vertical semiconductor pillar contacting the first contact;

a second contact located over the first vertical semiconductor pillar, wherein a second end of the first vertical semiconductor pillar contacts the second contact;

a second vertical semiconductor pillar located horizontally adjacent to the first vertical semiconductor pillar in a first row over the substrate;

a third vertical semiconductor pillar located horizontally adjacent to the first vertical semiconductor pillar in a second row different from the first row over the substrate;

third contacts coupling to the second vertical semiconductor pillar;

fourth contacts coupling to the third vertical semiconductor pillar;

a first charge storage region located adjacent to a first portion of a first side of the first vertical semiconductor pillar;

a second charge storage region located adjacent to a second portion of the first vertical semiconductor pillar above the first portion of the first vertical semiconductor pillar, wherein the first and second charge storage regions are two portions of a single contiguous material layer vertically extending from the first end of the first vertical semiconductor pillar to the second end of the first vertical semiconductor pillar;

a first control gate located adjacent to the first charge storage region;

a second control gate located adjacent to the second charge storage region;

a first tunneling dielectric layer located between the first side of the first vertical semiconductor pillar and the first charge storage region, between a bottom of the first charge storage region and the first contact, and between the first contact and the first control gate;

a first blocking dielectric layer located between the first charge storage region and the first control gate, and between the first contact and the first control gate; and

driver circuitry associated with the operation of the memory device;

wherein the first control gate is located entirely above the first contact;

wherein the first charge storage region comprises a dielectric charge storage layer; and

wherein the first control gate is shared between the first vertical semiconductor pillar, the second vertical semiconductor pillar and the third vertical semiconductor pillar.

10. The memory device of claim 9, wherein the first charge storage region comprises a silicon nitride layer and the first tunneling and blocking dielectric layers comprise silicon oxide layers.

11. The memory device of claim 10, wherein a portion of the silicon nitride layer extends under the first control gate between the first tunneling and the blocking dielectric layers, and a bottom of the first control gate is located on the first blocking dielectric layer above the first contact.

12. The memory device of claim 9, wherein the first tunneling dielectric layer is located on a top surface of the first contact under the bottom of the first charge storage region.

13. The memory device of claim 9, wherein the device comprises a three dimensional memory device, the first control gate is located adjacent to the first charge storage region in a first level, and the second control gate is located adjacent to the second charge storage region in a second level above the first level.

14. The memory device of claim 9, wherein the first control gate is located between the first vertical semiconductor pillar, the second vertical semiconductor pillar and the third vertical semiconductor pillar.

15. The memory device of claim 14, wherein:

the memory device further comprises a plurality of horizontally separated vertical semiconductor pillars;

the first control gate is shared between the plurality of horizontally separated vertical semiconductor pillars; and

the first control gate is located between the plurality of horizontally separated vertical semiconductor pillars.

16. The memory device of claim 15, wherein:

the plurality of horizontally separated vertical semiconductor pillars comprise a three by three array of horizontally separated vertical semiconductor pillars;

the first control gate is shared among the three by three array of horizontally separated vertical semiconductor pillars; and

the first control gate is located between the horizontally separated vertical semiconductor pillars of the three by three array of horizontally separated vertical semiconductor pillars.

17. The memory device of claim 15, wherein the plurality of horizontally separated vertical semiconductor pillars each have a substantially circular shape when viewed from above.

18. The memory device of claim 9, wherein the first vertical semiconductor pillar comprises substantially vertical sidewalls that extend from the first end of the first vertical semiconductor pillar to the second end of the first vertical semiconductor pillar, and the first vertical semiconductor pillar further comprises an additional first conductivity type semiconductor region located between the first conductivity type semiconductor region and said another first conductivity type semiconductor region, and all sidewalls of the additional first conductivity type semiconductor region are within the substantially vertical sidewalls of the first vertical semiconductor pillar.