Semiconductor device and manufacturing method of the same

• US 8,981,470 B2
• Filed: 03/06/2013
• Issued: 03/17/2015
• Est. Priority Date: 09/18/2012
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nozu, Tetsuro
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US13/787,628
• Publication Number:
  US 20140077278A1
• Time in Patent Office: 741 Days
• Field of Search: 257/331, 438/270
• US Class Current: 257/331
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The performance of power semiconductor device of partial gate type structure may be improved by providing the source region only adjacent the gate electrodes in the structure, and providing the contact spaced from the gate by the source. The device includes a plurality of field plate electrodes which extend inwardly of the drift layer, a second field plate electrode disposed between the contact and one of the first field plate electrodes, and a gate electrode located between the source and a second one of the first field plate electrode.

Claims

1. A semiconductor device comprising:

a drift layer;

a first and a second field plate electrode extending inwardly of the drift layer in a first direction and spaced from the drift layer by an insulating layer, the first and the second field plate electrodes being spaced from each other in a second direction perpendicular to the first direction;

a gate electrode extending inwardly of the drift layer in the first direction and between the first and the second field plate electrodes and spaced therefrom and from the drift layer by the insulating layer; and

a source region and a contact region, each of which is disposed between the first and second field plate electrodes in the second direction, wherein the contact region extends in the second direction from the source region to the insulating layer adjacent to the first field plate electrode.

2. The semiconductor device of claim 1, wherein the source region extends from the contact region to a portion of the insulating layer that is adjacent to the second field plate electrode.

3. The semiconductor device of claim 1, wherein a third field plate electrode is disposed within a portion of the insulating layer that is between the contact region and the first field plate electrode in the second direction.

4. The semiconductor device of claim 3, wherein the third field plate electrode and the contact region extend inwardly of the drift layer in the first direction to a first terminal position and a second terminal position, respectively;

a drain layer located on the drift layer on a side thereof opposed to the side thereof into which the field plate electrode inwardly extends; and

a distance from the first terminal position of the third field plate electrode to the drain layer is greater than a distance from the second terminal position of the contact region to the drain layer.

5. The semiconductor device of claim 3, wherein the gate electrode is disposed between the source region and the second field plate electrode.

6. The semiconductor device of claim 5, wherein the gate electrode is spaced from the source region and the second field plate electrode by the insulating layer.

7. The semiconductor device of claim 1, wherein the gate electrode is provided as a first gate electrode portion and a second gate electrode portion, and the first and second gate electrode portions are located on either side, in the second direction, of the second field plate electrode;

and

a third field plate electrode is between the first field plate electrode and the contact region.

8. The semiconductor device of claim 1, wherein a source electrode contacts the source region and the contact region, and the source region and contact region are differently doped.

9. The semiconductor device of claim 8, wherein the source electrode is spaced from the gate electrode and the first and second field plate electrodes by an interlayer insulating layer.

10. The semiconductor device of claim 8, wherein the insulating layer extends partially between the source and a drain layer in the first direction.

11. The semiconductor device of claim 9, wherein the interlayer insulating layer partially extends in the second direction between the second field plate electrode and the source electrode.

12. A semiconductor device comprising:

a first semiconductor layer of a first conductive type;

a second semiconductor layer of a second conductive type formed on the first semiconductor layer;

a first semiconductor region of the first conductive type formed on the second semiconductor layer;

a second semiconductor region of the second conductive type that comes in contact with the first semiconductor region formed on the second semiconductor layer, with the second semiconductor region having a higher concentration of impurity elements than in the second semiconductor layer;

a first electrode that comes in contact with the first semiconductor region, the second semiconductor layer and the first semiconductor layer through a first insulating layer;

a second electrode that comes in contact with second semiconductor region through a second insulating layer;

a third electrode connected to the first semiconductor region as well as the second semiconductor region; and

a fourth electrode electrically connected to the first semiconductor layer.

13. The semiconductor device according to claim 12, further comprising:

a pair of fifth electrodes in the first semiconductor region, the first electrode and the second electrode through a third insulating layer, wherein

a first width of the first semiconductor region, which is in a horizontal direction between the pair of fifth electrodes, and a second width of the second semiconductor region in this horizontal direction are the same magnitude.

14. The semiconductor device according to claim 13, wherein

a first length between a lower end of the second semiconductor region and a lower surface of the first semiconductor region is smaller than a second length between a lower end of the second electrode and the lower surface of the first semiconductor region.

15. The semiconductor device according to claim 12, wherein

the second electrode and a pair of fifth electrodes contact the third electrode.

16. A method of forming a power semiconductor device, comprising:

forming a drift layer;

forming a plurality of first field plate electrodes adjacent to and spaced from one another to extend inwardly of the drift layer;

forming secondary electrode structures on either side of at least two adjacent first field plate electrodes; and

on the portion of the drift layer between the at least two adjacent first field plate electrodes in the plurality of first field plate electrodes, forming a single contact region and a single source region, such that one of the secondary electrode structures is interposed between the single source region and a first one of the first field plate electrodes, and another of the secondary electrode structures is disposed between the single source region and a second one of the first field plate electrodes.

17. The method of forming a power semiconductor device according to claim 16, further including:

forming an insulating layer over the drift layer;

patterning the insulating layer to form an opening to expose only a portion of the single source region on the drift layer, the single source region being previously doped; and

doping the portion of the single source region differently than an unexposed portion of the single source region to form the single contact region.

18. The method of forming a power semiconductor device according to claim 17, further including:

increasing the size of the opening in the insulating layer to expose at least a second portion of the single source region in the enlarged opening after forming the single contact region.

19. The method of forming a power semiconductor device according to claim 17, wherein the secondary electrode structure disposed between the single source region and the first one of the first field plate electrode is a gate electrode.

20. The method of forming a power semiconductor device according to claim 17, wherein the single contact region is inwardly deeper in the drift layer than an adjacent one of the secondary electrode structures into the drift layer.