Optimization of loops and data flow sections in multi-core processor environment

• US 9,043,769 B2
• Filed: 12/28/2010
• Issued: 05/26/2015
• Est. Priority Date: 12/28/2009
• Status: Active Grant

• Current Assignee: Hyperion Core, Inc.
• Original Assignee: Hyperion Core, Inc.
• Inventors: Vorbach, Martin
• Primary Examiner(s): Khatri, Anil
• Application Number:
  US13/519,887
• Publication Number:
  US 20130191817A1
• Time in Patent Office: 1,610 Days
• Field of Search: 717140-144, 717148-151, 717154-156
• US Class Current: 717/149
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 8/41 Compilation
• CPC Class Codes: G06F 8/4441 Reducing the execution time required by the program code
• CPC Class Codes: G06F 8/452 Loops
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Claims

1. A method for executing a program on a processor the method comprising:

scheduling by a scheduler available processing hardware resources for executing at least one thread on at least one of a plurality of cores included in the processor,

each core having a multi-dimensional array of execution units and a register file, wherein the at least one thread is included in a plurality of threads partitioned from the program;

mapping the at least one thread for execution onto the hardware resources allocated by the scheduler;

configuring the interconnection between the execution units and the register file within one or more of the plurality of cores; and

creating one or more threads by the processor itself;

wherein creating one or more threads by the processor itself includes analyzing code by the processor.

2. The method of claim 1, wherein the scheduler is implemented in hardware.

3. The method of claim 1, wherein creating one or more threads by the processor itself includes detecting loops by the processor.

4. The method of claim 1, wherein creating one or more threads by the processor itself includes generating microcode for the one or more threads by the processor.

5. The method of claim 4, further comprising scheduling the one or more threads by the processor.

6. The method of claim 1, wherein the cores are Arithmetic Logic Unit (ALU) blocks.

7. The method of claim 1, wherein the one or more threads created by the processor include partitions of threads.