Processor-cache system and method

• US 9,047,193 B2
• Filed: 01/28/2011
• Issued: 06/02/2015
• Est. Priority Date: 01/29/2010
• Status: Active Grant

• Current Assignee: Shanghai Xin Hao Micro Electronics Co., Ltd.
• Original Assignee: Shanghai Xin Hao Micro Electronics Co., Ltd.
• Inventors: Lin, Kenneth Chenghao, Ren, Haoqi
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): RANKIN, CANDICE A
• Application Number:
  US13/520,572
• Publication Number:
  US 20130111137A1
• Time in Patent Office: 1,586 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/34 Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes address translation G06F12/00
• CPC Class Codes: G06F 9/355 Indexed addressing
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A digital system is provided. The digital system includes an execution unit, a level-zero (L0) memory, and an address generation unit. The execution unit is coupled to a data memory containing data to be used in operations of the execution unit. The L0 memory is coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory. The address generation unit is configured to generate address information for addressing the L0 memory. Further, the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.

Claims

1. A digital system, comprising:

an execution unit coupled to a data memory containing data to be used in operations of the execution unit;

a level-zero (L0) memory coupled between the execution unit and the data memory and configured to receive a part of the data in the data memory; and

an address generation unit configured to generate address information for addressing the L0 memory,

wherein the L0 memory provides at least two operands of a single instruction from the part of the data to the execution unit directly, without loading the at least two operands into one or more registers, using the address information from the address generation unit.

2. The system according to claim 1, wherein:

the L0 memory stores a result from the single instruction from the execution unit directly, without storing the result in a register, using the address information from the address generation unit.

3. The system according to claim 1, wherein:

the L0 memory includes a first memory and a second memory;

the first memory is coupled to the execution unit to provide one or more of the at least two operands; and

the second memory is coupled to the execution unit to receive the result and to provide one or more of the at least two operands.

4. The system according to claim 3, wherein:

the first memory is addressed by using at least one of an immediate direct addressing mode and a base address plus offset addressing mode.

5. The system according to claim 3, wherein:

the second memory is configured to store address information of the operands and corresponding operands, and the address information is content-addressable.

6. The system according to claim 5, wherein:

when the result corresponds to an address stored in the second memory, the stored operand corresponding to the address is updated to the result before being written back to the first memory.

7. The system according to claim 5, wherein:

the address information includes one of an actual address value, a base address value and an offset value, and a base pointer register number and an offset value.

8. The system according to claim 3, further including:

a third memory coupled to the execution unit and the first memory, wherein the execution unit is configured to obtain an operand from the third memory first and to obtain the operand from the first memory when the third memory does not contain the operand.

9. The system according to claim 3, wherein:

the first memory includes a first memory device with a first size and a second memory device with a second size, the first size being larger than the second size,

wherein the second memory device stores frequently-used data from the first memory device.

10. A multi-core processor comprising a plurality of serially-connected digital systems according to claim 3, wherein

an operation result written to a second memory of one digital system is provided to a first memory of a subsequent digital system such that the operation result is used in a multi-core operation.

11. The system according to claim 3, wherein:

the second memory includes a temporary storage space for storing temporary operation results that are not required to be written back to the first memory but are capable of being operands to the execution unit.

12. The system according to claim 3, wherein:

the execution unit is configured to accept an instruction including a bit indicating whether the result of the instruction needs to be written back to the first memory.

13. The system according to claim 3, wherein:

the execution unit is configured to accept an instruction including an opcode field, a first base address field, a first offset field, a second base address field, a second offset field, a result base address field, and a result offset field.