Method, system and medium for analog encryption in a flash memory

• US 9,104,610 B2
• Filed: 04/06/2011
• Issued: 08/11/2015
• Est. Priority Date: 04/06/2010
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: DensBits Technologies Ltd. (Broadcom, Inc.)
• Inventors: Weingarten, Hanan
• Primary Examiner(s): Hirl, Joseph P
• Assistant Examiner(s): NGUY, CHI D
• Application Number:
  US13/081,228
• Publication Number:
  US 20110302428A1
• Time in Patent Office: 1,588 Days
• Field of Search: 380/28, 380/277, 365/185.09, 365/185.33
• US Class Current: 1/1
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: H04L 9/065 Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
• CPC Class Codes: H04L 9/14 using a plurality of keys or algorithms

Abstract

A system and method for analog encryption and decryption, in which the encryption and encoding processes are interrelated, such that by failing to decrypt the retrieved data, decryption fails.

Claims

1. A method performed by a system that comprises hardware elements, the method comprising:

encrypting input data using a base key and an auxiliary key, wherein decryption of the encrypted input data requires the auxiliary key, and wherein the auxiliary key is only recoverable based on obtaining encrypted input data containing no errors;

modifying programming thresholds and incremental stepped pulse programming (ISPP) size of a Flash memory to increase a number of errors due to retention; and

storing the encrypted input data in the Flash memory;

wherein the encrypting of the input data comprises;

generating cipher data by performing a logical exclusive OR (XOR) operation on a key stream and an input data stream, wherein the key stream is dependent on a first encoding function;

generating intermediate encoded cipher data based on a second encoding function performed on the cipher data; and

generating final encoded cipher data based on the intermediate encoded cipher data and a result of the first encoding function;

wherein the method further comprises generating the key stream by;

performing the first encoding function on the base key to generate a codeword;

using the codeword to generate the auxiliary key and syndrome values;

performing a logical exclusive OR (XOR) operation on the auxiliary key and a cipher key to obtain a combined key; and

using the combined key to generate the key stream.

2. The method of claim 1, wherein the auxiliary key is obtained from a syndrome calculation of the entire codeword.

3. The method of claim 1, further comprising prior to storing the encrypted input data in the flash memory, cycling a Flash memory block that will store the encrypted input data such that following retention a number of errors occur in the encrypted input data to prohibit decoding.

4. A system, comprising:

a syndrome calculation unit arranged to generate an auxiliary key; and

a system portion that is arranged to encrypt input data using a base key and the auxiliary key, wherein decryption of the encrypted input data requires the auxiliary key, and wherein the auxiliary key is only recoverable based on obtaining encrypted input data containing no errors; and

a programming sequencer unit arranged to modify programming thresholds and incremental stepped pulse programming (ISPP) size of a Flash memory to increase a number of errors due to retention; and

store the encrypted input data in a Flash memory;

wherein at least one of the syndrome calculation unit and the programming sequencer unit is a hardware element;

a first exclusive OR (XOR) gate that is arranged to generate cipher data by performing a XOR operation on a key stream and an input data stream, wherein the key stream is dependent on a first encoding function;

a first encoder that is arranged to generate intermediate encoded cipher data based on a second encoding function performed on the cipher data;

a second XOR gate that is arranged to generate final encoded cipher data based on the intermediate encoded cipher data and a result of the first encoding function;

a second encoder that is arranged to perform the first encoding function on the base key to generate a codeword;

wherein the syndrome calculation unit is arranged to use the codeword to generate the auxiliary key and syndrome values;

wherein the first XOR gate is arranged to perform a logical exclusive OR (XOR) operation on the auxiliary key and a cipher key to obtain a combined key; and

and an encryption module that is arranged to use the combined key to generate the key stream.

5. The system of claim 4, wherein the syndrome calculation unit is arranged to obtain the auxiliary key from a syndrome calculation of the entire codeword.

6. The system of claim 4, wherein prior to causing the encoded input data to be stored in the flash memory the programming sequencer unit is configured to cycle a Flash memory block that will store the encrypted input data such that following retention a number of errors occur in the encrypted input data to prohibit decoding.