Passive integrated circuit

• US 9,117,693 B2
• Filed: 06/08/2011
• Issued: 08/25/2015
• Est. Priority Date: 06/10/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Laporte, Claire, Ezzeddine, Hilal
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Malek, Maliheh
• Application Number:
  US13/155,533
• Publication Number:
  US 20110304014A1
• Time in Patent Office: 1,539 Days
• Field of Search: 438/381, 438/393, 257/528, 257531-533, 257/535, 257/E27.009, 257/E27.113, 257/E21.022
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H03H 5/02 : without voltage- or current-dependent elements

Abstract

A passive integrated circuit formed on a substrate, including contact areas of a conductive material specifically capable of receiving bonding pads, wherein the conductive material further creates connections between regions of a lower metallization level.

Claims

1. A passive integrated circuit comprising:

a substrate;

a first layer of conductive material being on said substrate, said first layer of conductive material defining an inductor, and upper electrodes of a plurality of capacitors;

a second layer of a conductive material

being above and in contact with said first layer of conductive material, and

comprising a plurality of contact areas configured to receive a plurality of bonding pads,

said second layer of conductive material comprising a stack of a titanium layer, a nickel layer, a copper layer, and a gold layer;

said second layer of conductive material defining connections between separated regions of the inductor and defining connections between the upper electrodes of the plurality of capacitors.

2. The circuit of claim 1, wherein the inductor comprises a winding;

and wherein said second layer of conductive material defines a connection between an end of the winding and a component.

3. The circuit of claim 1, wherein said second layer of conductive material has a thickness of about 1.5 μ

m.

4. The circuit of claim 1, wherein the first layer of conductive material comprises copper.

5. A method for making a passive integrated circuit, the method comprising:

forming, at a substrate, first conductive regions of a first metallization layer;

forming an inductor and upper electrodes of a plurality of capacitors only in the first metallization layer; and

forming, above the first metallization layer, second conductive regions of a second layer of conductive material capable of receiving a plurality of bonding pads, the second conductive regions having portions in direct physical contact with the first metallization layer;

said second layer of conductive material comprising a stack of a titanium layer, a nickel layer, a copper layer, and a gold layer, the second conductive regions

defining connections between separated regions of the inductor formed in the first metallization layer, and

defining connections between the upper electrodes of the plurality of capacitors formed in the first metallization layer.

6. The method of claim 5, wherein the inductor comprises a winding, said second conductive regions creating a connection between an end of the winding and a component of the passive integrated circuit.

7. The method of claim 5, wherein the first metallization layer comprises copper.

8. The method of claim 5, further comprising at the design level, decreasing a length of the connections.

9. A method for forming a passive integrated circuit, the method comprising:

depositing a first metallization layer;

forming an inductor winding in the first metallization layer;

forming upper electrodes of a plurality of capacitors in the first metallization layer;

depositing a second metallization layer comprising a stack of a titanium layer, a nickel layer, a copper layer, and a gold layer;

at least one portion of the second metallization layer being in direct physical contact with the first metallization layer and coupling at least two separated elements of the inductor and the upper electrodes of the plurality of capacitors; and

forming a plurality of contact pads for receiving a plurality of bonding pads in the second metallization layer and being beneath an insulating layer, the plurality of contact pads to be accessed through a plurality of vias in the insulating layer.

10. The method of claim 9, further comprising depositing copper as the first metallization layer.

11. The method of claim 10, further comprising depositing the copper to a thickness of about 6 microns.

12. The method of claim 9, further comprising depositing the second metallization layer to a thickness of about 1.5 microns.

13. The method of claim 9, further comprising:

depositing the insulating layer over the second metallization layer; and

forming the plurality of vias through the insulating layer to expose the plurality of contact pads.

14. The circuit of claim 9, wherein the plurality of contact pads do not extend onto sidewalls of the plurality of vias.