Thin film transistor including semiconductor oxide layer having reduced resistance regions

• US 9,123,820 B2
• Filed: 03/02/2011
• Issued: 09/01/2015
• Est. Priority Date: 05/31/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Katoh, Sumio
• Primary Examiner(s): GORDON, MATTHEW E
• Application Number:
  US13/640,354
• Publication Number:
  US 20130048998A1
• Time in Patent Office: 1,644 Days
• Field of Search: 257/59, 257/E29.151, 438/149
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device (S_T) includes a substrate (11), a gate electrode (12b), a gate insulating film (13b), an oxide semiconductor film (14b) including a channel part (14bc) formed in a position facing the gate electrode (12b), a source electrode (15bs), and a drain electrode (15bd). The source electrode (15bs) and the drain electrode (15bd) is arranged so as not to overlap with the gate electrode (12b) as viewed in the plane. A region adjacent to the gate electrode (12b) and the source electrode (15bs) and a region adjacent to the gate electrode (12b) and the drain electrode (15bd) are, in a region where the source electrode (15bs) and the drain electrode (15bd) does not overlap with the gate electrode (12b), processed such that resistance in a region of the oxide semiconductor film (14b) including a surface thereof is reduced.

Claims

1. A semiconductor device, comprising:

a substrate;

a gate electrode provided on the substrate;

a gate insulating film provided so as to cover the gate electrode;

an oxide semiconductor film provided on the gate insulating film and including a channel portion having a channel sheet resistance and arranged in a position facing the gate electrode; and

a source electrode and a drain electrode provided apart from each other on the oxide semiconductor film with the channel part being interposed between the source electrode and the drain electrode, wherein

at least one of the source electrode and the drain electrode is arranged so as not to overlap with the gate electrode as viewed in a plan view,

the oxide semiconductor film further includes a first portion having a first sheet resistance, which is smaller than the channel sheet resistance, the first portion extends from an edge of the at least one of the source electrode and the drain electrode towards the channel portion, and the first portion is overlapped by the gate electrode, and

the oxide semiconductor film further includes a second portion having a second sheet resistance, which is larger than the first sheet resistance, the second portion being located beneath the at least one of the source electrode and the drain electrode.

2. The semiconductor device of claim 1, wherein

the first sheet resistance of the first region of the oxide semiconductor film is 10 Ω

/sq-100 kΩ

/sq.

3. The semiconductor device of claim 1, wherein

the channel portion includes a channel width of equal to or less than 50 μ

m.

4. The semiconductor device of claim 1, wherein

the oxide semiconductor film is made of metal oxide containing at least one selected from a group consisting of indium (In), gallium (Ga), and zinc (Zn).

5. The semiconductor device of claim 4, wherein the oxide semiconductor film is made of In—

Ga—

Zn—

O metal oxide.

6. A thin film transistor substrate, comprising:

a thin film transistor provided on a substrate body,

wherein the thin film transistor is the semiconductor device of claim 1.

7. The thin film transistor substrate of claim 6, wherein

the semiconductor device is provided at a last stage of a buffer circuit of a gate driver region.

8. A display apparatus, comprising:

the thin film transistor substrate of claim 6;

a counter substrate arranged so as to face the thin film transistor substrate; and

a display medium layer provided between the thin film transistor substrate and the counter substrate.

9. The display apparatus of claim 8, wherein

the display medium layer is a liquid crystal layer.

10. The semiconductor device of claim 1, wherein a position of an edge of the first portion which is opposite to the channel portion is located at substantially the same position as the edge of the at least one of the source electrode and the drain electrode when viewed in the plan view.

11. The semiconductor device of claim 1, wherein an edge of the first portion which is opposite to the channel portion is extended beneath the at least one of the source electrode and the drain electrode.

12. A display apparatus, comprising:

a first substrate;

a first transistor provided in a display region of the display apparatus;

a second transistor included in a peripheral driver circuit which is positioned outside of the display region;

the first transistor including;

a first gate electrode provided on the first substrate;

a first gate insulating film provided so as to cover the first gate electrode;

a first oxide semiconductor film provided on the first gate insulating film and including a first channel portion arranged in a position facing the first gate electrode; and

a first source electrode and a first drain electrode provided apart from each other on the first oxide semiconductor film with the first channel portion being interposed between the first source electrode and the first drain electrode;

wherein the second transistor including;

a second gate electrode provided on the first substrate;

a second gate insulating film provided so as to cover the second gate electrode;

a second oxide semiconductor film provided on the second gate insulating film and including a second channel portion having a channel sheet resistance and arranged in a position facing the second gate electrode; and

a second source electrode and a second drain electrode provided apart from each other on the second oxide semiconductor film with the second channel portion being interposed between the second source electrode and the second drain electrode;

wherein

the first source electrode and the first drain electrode are overlapped with the first gate electrode when viewed in a plan view;

at least one of the second source electrode and the second drain electrode is arranged so as not to overlap with the second gate electrode as viewed in the plan view;

the second oxide semiconductor film further includes a first portion having a first sheet resistance, which is smaller than the channel sheet resistance, the first portion extends from an edge of the at least one of the second source electrode and the second drain electrode towards the second channel portion, and the first portion is overlapped by the second gate electrode; and

the second oxide semiconductor film further includes a second portion having a second sheet resistance, which is larger than the first sheet resistance, the second portion being located beneath the at least one of the second source electrode and the second drain electrode.

13. The display apparatus of claim 12, wherein sheet resistance in the region of the second oxide semiconductor film where the resistance is reduced is 10 Ω

/sq-100 kΩ

/sq.

14. The display apparatus of claim 12, wherein the second channel portion has a channel width of equal to or less than 50μ

m.

15. The display apparatus of claim 12, wherein the first and second oxide semiconductor films are made of metal oxide containing at least one selected from a group consisting of indium (In), gallium (Ga), and zinc (Zn).

16. The display apparatus of claim 15, wherein the first and second oxide semiconductor films are made of In—

Ga—

Zn—

O metal oxide.

17. The display apparatus of claim 12, wherein the second transistor is provided at a last stage of a buffer circuit of a gate driver region.

18. The display apparatus of claim 12, further comprising:

a second substrate arranged so as to face the first substrate; and

a display medium layer provided between the first substrate and the second substrate.

19. The display apparatus of claim 18, wherein the display medium layer is a liquid crystal layer.