Portable device with dual image sensors and quad-core processor

• US 9,143,636 B2
• Filed: 09/15/2012
• Issued: 09/22/2015
• Est. Priority Date: 07/15/1997
• Status: Expired due to Fees

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Silverbrook, Kia
• Primary Examiner(s): GILES, NICHOLAS G
• Application Number:
  US13/621,019
• Publication Number:
  US 20130010083A1
• Time in Patent Office: 1,102 Days
• US Class Current: 1/1
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• CPC Class Codes: B41J 11/005 Guides in the printing zone, e.g. guides for preventing contact of conveyed sheets with printhead
• CPC Class Codes: B41J 11/70 cutting perpendicular to the direction of paper feed
• CPC Class Codes: B41J 15/04 Supporting, feeding, or guiding devices; Mountings for web rolls or spindles
• CPC Class Codes: B41J 2/14314 Structure of ink jet print heads with electrostatically actuated membrane
• CPC Class Codes: B41J 2/14427 Structure of ink jet print heads with thermal bend detached actuators
• CPC Class Codes: B41J 2/16585 for paper-width or non-reciprocating print heads
• CPC Class Codes: B41J 2/17513 Inner structure
• CPC Class Codes: B41J 2/17596 Ink pumps, ink valves
• CPC Class Codes: B41J 2002/041 Electromagnetic transducer
• CPC Class Codes: B41J 2202/21 Line printing
• CPC Class Codes: B41J 3/445 Printers integrated in other types of apparatus, e.g. printers integrated in cameras
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: G06F 15/00 Digital computers in general details G06F1/00 – G06F13/00; Data processing equipment in general
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• CPC Class Codes: G06F 2221/2129 Authenticate client device independently of the user
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
• CPC Class Codes: G06F 9/265 by address selection on input of storage
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• CPC Class Codes: H04N 1/00127 : Connection or combination of a still picture apparatus with another apparatus, e.g. for storage, processing or transmission of still picture signals or of information associated with a still picture
• CPC Class Codes: H04N 1/00278 : with a printing apparatus, e.g. a laser beam printer
• CPC Class Codes: H04N 1/00326 : with a data reading, recognizing or recording apparatus, e.g. with a bar-code apparatus arrangements for the associated working of recording or reproducing apparatus with related apparatus G11B31/00
• CPC Class Codes: H04N 1/0044 : for image preview or review, e.g. to help the user position a sheet
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• CPC Class Codes: H04N 5/76 : Television signal recording

Abstract

A portable device that has first and second image sensors and a central processor. The central processor has four processing units and a first image sensor interface and a second image sensor interface for receiving data from the from the first and second image sensors respectively. The four processing units and the first and second sensor interfaces are integrated onto a single chip such that the four processing units are configured to simultaneously process the data from the first and second image interfaces to generate stereoscopic image data.

Claims

1. An electronic device, comprising:

a first image sensor;

a second image sensor; and

a processor including;

a first image sensor interface for receiving data from the from the first image sensor,

a second image sensor interface for receiving data from the from the second image sensor,

multiple processing units configured to process data in parallel based on executing image processing instructions, and

an instruction input interface configured to receive a signal based on a pattern and to decode the signal into the image processing instructions,

wherein the multiple processing units are configured to simultaneously process the data from the first and second image interfaces to generate stereoscopic image data.

2. The electronic device according to claim 1, wherein the processor further comprises a crossbar switch for interconnecting each of the multiple processing units.

3. The electronic device according to claim 1, wherein the processor further includes:

an input FIFO (first in, first out) configured to receive data from the first and second image sensor interfaces and input the data to the multiple processing units; and

an output FIFO configured to receive processed data to be read by other components of the electronic device.

4. The electronic device according to claim 3, wherein the processor further includes:

a central processing unit; and

a data bus connecting the central processing unit to the input FIFO and the output FIFO, the central processing unit providing a processing core to operatively control the multiple processing units.

5. The electronic device according to claim 4, wherein the processor further includes a data cache to store the processed data until required by the central processing unit.

6. The electronic device according to claim 1, wherein the multiple processing units are further configured to perform one or more processing tasks selected from:

rotating the data received from the first and second image sensors;

color converting the data received from the first and second image sensors; and

dithering the data received from the first and second image sensors.

7. The electronic device according to claim 1, further comprising a display for viewing an image captured by the first and second image sensors, wherein the processor further includes a display interface for transmitting processed data to the display.

8. The electronic device according to claim 5, wherein each of the multiple processing units includes at least one address generator for the processed data sent to the data cache.

9. The electronic device according to claim 4, wherein each of the multiple processing units has RAM (random access memory) for storing microcode written by the central processing unit to operatively control the processing unit.

10. The electronic device according to claim 9, wherein the processor further includes a keyboard interface for user input of instructions to the central processing unit such that the central processing unit rewrites the microcode in the RAM within each of the multiple processing units.

11. The electronic device according to claim 1, further comprising a USB port for communication with an external device, wherein the processor further comprises a USB interface.

12. The electronic device according to claim 1, further comprising a 3 Volt battery.

13. A processor, comprising:

a first image sensor interface for receiving data from a first image sensor;

a second image sensor interface for receiving data from a second image sensor;

multiple processing units configured to process data in parallel based on executing image processing instructions; and

an instruction input interface configured to receive a signal based on a pattern and to decode the signal into the image processing instructions,

wherein the multiple processing units are configured to simultaneously process the data from the first and second image interfaces to generate stereoscopic image data.

14. The processor according to claim 13, further comprising a crossbar switch for interconnecting each of the multiple processing units.

15. The processor according to claim 13, further comprising:

an input FIFO (first in, first out) configured to receive data from the first and second image sensor interfaces and input the data to the multiple processing units; and

an output FIFO configured to receive processed data to be read by other components of the electronic device.

16. The processor according to claim 15, further comprising:

a central processing unit; and

a data bus connecting the central processing unit to the input FIFO and the output FIFO, the central processing unit providing a processing core to operatively control the multiple processing units.

17. The processor according to claim 16, wherein each of the multiple processing units has RAM (random access memory) for storing microcode written by the central processing unit to operatively control the processing unit.

18. The processor according to claim 17, wherein the processor further includes a keyboard interface for user input of instructions to the central processing unit such that the central processing unit rewrites the microcode in the RAM within each of the multiple processing units.

19. The processor according to claim 16, further comprising a data cache to store the processed data until required by the central processing unit.

20. The electronic device according to claim 19, wherein each of the multiple processing units includes at least one address generator for the processed data sent to the data cache.