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High capacity memory system using standard controller component

  • US 9,165,639 B2
  • Filed: 11/11/2014
  • Issued: 10/20/2015
  • Est. Priority Date: 11/11/2013
  • Status: Active Grant
First Claim
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1. A system comprising:

  • a motherboard substrate;

    a memory controller disposed on the motherboard substrate;

    a memory module disposed on the motherboard substrate and coupled to the memory controller;

    wherein the memory module comprises;

    a plurality of device sites; and

    a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links;

    at least eighteen dynamic random access memory (DRAM) devices disposed at respective device sites;

    nine DQ buffer components coupled to the at least eighteen DRAM devices, each of the nine DQ buffer components being coupled to a respective pair of the at least eighteen DRAM devices, wherein the nine DQ buffer components includes the DQ buffer component; and

    a command and address (CA) buffer component coupled to the at least eighteen DRAM devices.

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