Reset supervisor
First Claim
Patent Images
1. A method comprising:
- (a) receiving an input signal at a first processor and at a second processor;
(b) at the first processor, processing the input signal to generate an output signal;
(c) transmitting the output signal from the first processor to the second processor;
(d) at the second processor, comparing the input signal to the output signal and determining that an error exists when the input signal does not correspond to the output signal;
(e) when an error exists in (d), transmitting a reset signal from the second processor to the first processor to reset the first processor; and
(f) loading firmware into the first processor in response to receiving the reset signal at the first processor.
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Accused Products
Abstract
Multiple processor systems are provided. A first processor is configured to monitor the state of at least one other processor by comparing received signals. When the first processor determines that another processor needs to be reset, the first processor provides a reset signal to a reset pin of the processor that needs to be reset. The first processor may reset itself after providing the reset signal.
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Citations
17 Claims
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1. A method comprising:
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(a) receiving an input signal at a first processor and at a second processor; (b) at the first processor, processing the input signal to generate an output signal; (c) transmitting the output signal from the first processor to the second processor; (d) at the second processor, comparing the input signal to the output signal and determining that an error exists when the input signal does not correspond to the output signal; (e) when an error exists in (d), transmitting a reset signal from the second processor to the first processor to reset the first processor; and (f) loading firmware into the first processor in response to receiving the reset signal at the first processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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(a) receiving an input signal at a first processor and at a second processor; (b) at the first processor, processing the input signal to generate an output signal; (c) transmitting the output signal from the first processor to the second processor; (d) at the second processor, comparing the input signal to the output signal and determining that an error exists when the input signal does not correspond to the output signal; (e) receiving a user input at the second processor; and (f) when an error exists in (d), transmitting a reset signal from the second processor to the first processor to reset the first processor in a manner determined by the user input. - View Dependent Claims (11)
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12. A method of monitoring and resetting a processor, the method comprising:
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(a) receiving, from a port, at least one bus signal at a first processor and at a second processor; (b) at the second processor, determining that an error exists when the first processor does not provide the at least one bus signal to the second processor; and (c) when an error exists in (b), transmitting a reset signal from the second processor to the first processor; and (d) loading firmware into the first processor in response to receiving the reset signal at the first processor. - View Dependent Claims (13, 14, 15)
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16. A non-transitory computer-readable storage medium that contains computer-executable instructions that when executed cause a processor to perform steps comprising:
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(a) receiving, from a port, at least one bus signal; (b) receiving, from another processor, at least one bus signal; (c) determining that an error condition exists when the bus signals received in (a) and in (b) do not correspond; (d) when an error condition exists, transmitting a reset signal to said another processor; and (e) loading firmware into said another processor in response to receiving the reset signal at said another processor. - View Dependent Claims (17)
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Specification