Apparatuses and methods to modify pillar potential

• US 9,171,625 B2
• Filed: 06/15/2012
• Issued: 10/27/2015
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji, Feeley, Peter Sean
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US13/525,035
• Publication Number:
  US 20130336070A1
• Time in Patent Office: 1,229 Days
• Field of Search: 365/185.11, 365/185.22, 365/185.17, 365/185.05, 257/315
• US Class Current: 1/1
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.

Claims

1. A method comprising:

performing a first operation on a first charge storage device in a block of charge storage devices, some of the charge storage devices in the block being associated with a pillar comprising semiconductor material;

inducing drain leakage current in a select gate transistor of the pillar to modify an electrical potential of the pillar; and

performing a second operation on a second charge storage device in the block of charge storage devices.

2. The method of claim 1, wherein inducing drain leakage current further comprises raising the electrical potential of the pillar.

3. The method of claim 1, wherein inducing drain leakage current further comprises lowering the electrical potential of the pillar.

4. The method of claim 1, wherein inducing drain leakage current further comprises causing electrical current to flow into the pillar.

5. The method of claim 1, wherein inducing drain leakage current further comprises causing excess holes in the pillar to be absorbed.

6. An apparatus comprising:

a string of charge storage devices comprising a plurality of charge storage devices and a select gate transistor associated with a pillar comprising semiconductor material;

a cap comprising semiconductor material and coupled to the pillar to form a p-n junction between the cap and the pillar;

a plurality of access lines associated with the string; and

a charge pump circuit coupled to the cap and configured to selectively cause drain leakage current to be induced in the select gate transistor to modify an electrical potential of the pillar after a first memory operation and prior to a second memory operation.

7. The apparatus of claim 6, wherein the select gate transistor comprises a source select gate transistor, the pillar comprises p-type semiconductor material, the cap comprises n-type semiconductor material, and wherein the string further comprises a drain select gate transistor.

8. The apparatus of claim 6, wherein each of the access lines at least partially surrounds a respective one of the charge storage devices and the pillar.

9. The apparatus of claim 6, wherein at least some of the charge storage devices comprise charge trap transistors.

10. The apparatus of claim 6, wherein at least some of the charge storage devices comprise floating gate transistors.

11. The apparatus of claim 6, wherein the apparatus comprises a system.

12. The apparatus of claim 6, wherein the apparatus comprises a memory device.

13. The apparatus of claim 6, wherein the select gate transistor comprises a source select gate transistor at least partially surrounding the pillar and configured to selectively couple the pillar to a source, and wherein the pillar further comprises a drain select gate transistor at least partially surrounding the pillar and configured to selectively couple the pillar to a data line.

14. A method comprising:

performing a first read operation on a charge storage device in a block of charge storage devices, each of the charge storage devices in the block being associated with a respective one of a plurality of pillars, each pillar comprising semiconductor material;

inducing drain leakage current in a select gate transistor of a selected one of the pillars to modify an electrical potential of the selected pillar; and

performing a second read operation on a charge storage device in the block of charge storage devices.

15. The method of claim 14, wherein inducing drain leakage current further comprises raising the electrical potential of the selected pillar.

16. The method of claim 14, wherein inducing drain leakage current comprises raising an electrical potential of a cap coupled to the selected pillar to induce gate-induced drain leakage (GIDL) current in the selected pillar, the selected pillar comprising semiconductor material and the cap comprising semiconductor material.

17. The method of claim 16, wherein inducing drain leakage current comprises inducing GIDL current in a source select gate transistor at least partially surrounding the selected pillar.

18. The method of claim 14, wherein inducing drain leakage current further comprises modifying an electrical potential of selected ones of the pillars that are floating during the first read operation.

19. A method comprising:

performing a first operation on a selected charge storage device in a block of charge storage devices, some of the charge storage devices in the block being associated with a pillar comprising semiconductor material;

lowering an electrical potential of the pillar; and

performing a read operation on the selected charge storage device in the block of charge storage devices.

20. The method of claim 19, wherein performing a first operation further comprises performing a plurality of page read operations on charge storage devices in the block of charge storage devices.

21. The method of claim 19, wherein performing a first operation further comprises performing a read operation on the selected charge storage device in the block of charge storage devices.

22. The method of claim 19, wherein lowering an electrical potential of the pillar further comprises forward biasing a p-n junction between a cap and the pillar.

23. The method of claim 19, wherein lowering an electrical potential of the pillar further comprises lowering an electrical potential of an n+ type cap coupled to the pillar to absorb holes in the cap, the pillar comprising a p+-type semiconductor material.

24. The method of claim 23, wherein lowering the electrical potential of the n+ type cap further comprises lowering the electrical potential of the n+ type cap with a charge pump circuit.

25. A method comprising:

performing a read operation on a charge storage device in a block of charge storage devices, some of the charge storage devices in the block being associated with a respective one of a plurality of pillars, each pillar comprising semiconductor material;

inducing drain leakage current in a select gate transistor of a selected one of the pillars to raise an electrical potential of the selected pillar; and

performing an erase operation on a charge storage device in the block of charge storage devices.

26. The method of claim 25, wherein inducing drain leakage current further comprises raising an electrical potential of a source coupled to the select gate transistor to induce GIDL current in the pillar.

27. The method of claim 26, wherein inducing drain leakage current further comprises inducing GIDL current in a source select gate transistor at least partially surrounding the selected pillar.

28. The method of claim 26, wherein inducing drain leakage current further comprises inducing GIDL current in a drain select gate transistor at least partially surrounding the selected pillar.

29. The method of claim 26, wherein raising the electrical potential of a source coupled to the select gate transistor comprises raising the electrical potential with a charge pump circuit.

30. The method of claim 25, wherein inducing drain leakage current further comprises raising an electrical potential of selected ones of the pillars that are floating during the read operation.

31. A method comprising:

performing a programming operation on a charge storage device in a block of charge storage devices, some of the charge storage devices in the block being associated with a respective one of a plurality of pillars, each pillar comprising semiconductor material;

inducing drain leakage current in a select gate transistor of a selected one of the pillars to modify an electrical potential of the selected pillar; and

performing a program verify operation on the charge storage device.

32. The method of claim 31, wherein inducing drain leakage current in a select gate transistor of a selected one of the pillars to modify an electrical potential of the selected pillar comprises raising the electrical potential of the selected pillar.

33. The method of claim 31, wherein inducing drain leakage current further comprises raising the electrical potential of a pillar associated with the charge storage device.

34. The method of claim 31, wherein inducing drain leakage current further comprises modifying an electrical potential of selected ones of the pillars that were floating during the programming operation.

35. The method of claim 31, further comprising modifying an electrical potential of a selected one of the pillars after the program verify operation.