Circuit having a low power mode

• US 9,189,048 B2
• Filed: 09/10/2008
• Issued: 11/17/2015
• Est. Priority Date: 09/10/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wilson, Thomas James, Krah, Christoph Horst, Hotelling, Steve Porter
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US12/208,311
• Publication Number:
  US 20100064160A1
• Time in Patent Office: 2,624 Days
• Field of Search: 713/300, 713/320, 713/323, 713/324
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake

Abstract

Embodiments of the invention include an IC that includes a core used for ordinary operation and a thin power circuit. The thin power circuit can be configured to use very little power. The IC can also include a digital interface and a connection thereto. The IC can initiate transition to low power mode during which the core and various I/O pads can be shut down. However, the thin power circuit can be kept powered up. The thin power circuit can monitor the digital interface for a predefined wake up signal. When the wake up signal is detected, the thin power circuit can power up the core and any powered down I/O pads. The thin power circuit can also include a dedicated power on reset (POR) cell. This POR cell can be distinct than other POR cells used for the IC and can be specifically designed to for efficient operation.

Claims

1. An integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising:

a digital interface;

a digital input connected to the digital interface;

a configuration memory configured to store configuration information defining a configuration of the IC;

primary operation circuitry connected to the digital interface and configured to perform one or more primary tasks, the primary operation circuitry configured for selectively having at least a portion of its power removed during a low power mode; and

a first power manager connected to the primary operation circuitry and the digital input, the first power manager configured to receive a set of one or more predefined digital signals over the digital input during the low power mode, change the information stored in the configuration memory, and initiate a power up of the primary operation circuitry in response to the set of predefined digital signals;

wherein the primary operation circuitry includes a second power manager configured to be powered down during the low power mode, and further configured to be powered up and perform power up operations on the primary operation circuitry in response to a signal from the first power manager.

2. The IC of claim 1, wherein the digital interface is configured to transmit and receive digital data according to a predefined digital transmission standard, and the set of predefined digital signals is in accordance with the predefined digital transmission standard.

3. The IC of claim 2, wherein the predefined digital transmission standard is the Serial Peripheral Interface (SPI) standard.

4. The IC of claim 3, wherein the set of predefined digital signals is a valid SPI frame.

5. The IC of claim 2, wherein the predefined digital transmission standard includes one or more standards selected from the group consisting of the low-voltage differential signaling (LVDS), transition minimized differential signaling (TMDS), universal serial bus (USB), Firewire and PCI Express standards.

6. The IC of claim 1, wherein the IC is configured to remove all power from the primary operation circuitry.

7. The IC of claim 1, wherein the first power manager is configured to remove substantially all power from the primary operation circuitry.

8. The IC of claim 1, wherein the first power manager includes a primary state flip flop the primary state flip flop having a first and a second state, the primary state flip flop being in the first state during a first time period when the primary operation circuitry is fully powered and in ordinary operation and in the second state during a second time period when power is removed from the primary operation circuitry, wherein the first and second time periods do not include any transition periods during which the primary operation circuitry is in the process of being powered up, or having power removed therefrom.

9. The IC of claim 8, wherein the primary state flip flop causes the first power manager to ignore signals arriving from the digital input when the primary state flip flop is in the first state and to monitor the digital input for the set of predefined digital signals when the primary state flip flop is in the second state.

10. The IC of claim 1, wherein the digital input includes a plurality of digital connections and the set of predefined digital signals includes a plurality of digital signals received at respective ones of the plurality of digital connections.

11. The IC of claim 1, wherein the first power manager includes one or more inputs connected to the primary operation circuitry, said inputs being used to receive signals indicating an upcoming removal of power from the primary operation circuitry, the first power manager further including one or more resistive pull downs connected to the one or more inputs connected to the primary operation circuitry.

12. The IC of claim 11, wherein the primary operation circuitry is configured to keep the one or more inputs connected to the primary operation circuitry at a low or ground voltage level for most of the time, setting them to a high voltage level only during relatively short pulses.

13. The IC of claim 1, wherein the second power manager is configured to perform complex power up and power down procedures, and to lose substantially all power when substantially all power is removed from the primary operation circuitry.

14. The IC of claim 13, wherein the first power manager uses substantially less power than the second power manager.

15. The IC of claim 1, wherein the first power manger uses substantially less power than the primary operation circuitry.

16. The IC of claim 1, wherein the set of one or more predefined digital signals includes a payload portion and an error checking portion, and the first power manager is configured to check the payload portion based on the error checking portion before powering up the primary operation circuitry.

17. A portable audio player including an integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising:

a digital interface;

a digital input connected to the digital interface;

a configuration memory configured to store configuration information defining a configuration of the IC;

primary operation circuitry configured to perform one or more primary tasks and connected to the digital interface, the IC being configured to selectively remove at least a portion of its power from the primary operation circuitry during a low power mode; and

a first power manager connected to the primary operation circuitry and the digital input, the first power manager configured to

receive a set of one or more predefined digital signals over the digital input during the low power mode,

in response to the set of predefined digital signals, change the information stored in the configuration memory, and initiate a power up of the primary operation circuitry;

wherein the primary operation circuitry includes a second power manager configured to be powered down during the low power mode, and further configured to be powered up and perform power up operations on the primary operation circuitry in response to a signal from the first power manager.

18. A mobile telephone including an integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising:

a digital interface;

a digital input connected to the digital interface;

a configuration memory configured to store configuration information defining a configuration of the IC;

primary operation circuitry configured to perform one or more primary tasks and connected to the digital interface, the IC being configured to selectively remove at least a portion of its power from the primary operation circuitry during a low power mode; and

a first power manager connected to the primary operation circuitry and the digital input, the first power manager configured to

receive a set of one or more predefined digital signals over the digital input during the low power mode, and

in response to the set of predefined digital signals, change the information stored in the configuration memory, and initiate a power up of the primary operation circuitry;

wherein the primary operation circuitry includes a second power manager configured to be powered down during the low power mode, and further configured to be powered up and perform power up operations on the primary operation circuitry in response to a signal from the first power manager.

19. A method for operating an integrated circuit (IC) including primary operation circuitry including a digital interface, a digital input connected to the digital interface, a configuration memory configured to store configuration information defining a configuration of the IC, a second power manager dedicated for managing power of the primary operation circuitry and configured to be powered down during the low power mode, and a first power manager, the method comprising:

powering down at least a portion of the primary operation circuitry including the second power manager during a low power mode while keeping the first power manager powered;

receiving a set of one or more predefined digital signals over the digital input by the first power manger during the low power mode; and

in response to the set of predefined digital signals, initiating a power up of the primary operation circuitry by the first power manager, including

changing the information stored in the configuration memory and

powering up the second power manager in response to a signal from the first power manager, and

powering up the primary operation circuitry by the second power manager.

20. The method of claim 19, further comprising receiving the set of one or more predefined digital signals in accordance with a predefined digital transmission standard.

21. The method of claim 20, wherein the predefined digital transmission standard is the Serial Peripheral Interface (SPI) standard.

22. The method of claim 21, wherein the set of predefined digital signals is a valid SPI frame.

23. The method of claim 19, wherein powering down the primary operation circuitry includes removing substantially all power from the primary operation circuitry.

24. The method of claim 19, wherein powering down the primary operation circuitry includes removing all power from the primary operation circuitry.

25. The method of claim 19, wherein the powering down the primary operation circuitry is performed at least partially by the first power manager.

26. The method of claim 19, wherein the first power manager includes a primary state flip flop the primary state flip flop having a first and a second state, the primary state flip flop being in the first state during a first time period when the primary operation circuitry is fully powered and in ordinary operation and in the second state during a second time period when power is removed from the primary operation circuitry, wherein the first and second time periods do not include any transition periods during which the primary operation circuitry is in the process of being powered up, or having power removed therefrom.

27. The method of claim 26, further comprising:

ignoring signals arriving from the digital input when the primary state flip flop is in the first state; and

monitoring the digital input for the set of predefined digital signals when the primary state flip flop is in the second state.

28. The method claim 19, wherein the digital input includes a plurality of digital connections and the set of predefined digital signals includes a plurality of digital signals received at respective ones of the plurality of digital connections.

29. The method of claim 19, wherein the first power manager includes one or more inputs connected to the primary operation circuitry, the method further comprising:

receiving signals by the first power manager from the one or more inputs connected to the primary operation circuitry, the signals indicating an upcoming removal of power from the primary operation circuitry;

setting the one or more inputs connected to the primary operation circuitry to a low or ground voltage when the primary operation circuitry is powered down by using resistive pull downs connected to the one or more inputs connected to the primary operation circuitry.

30. The method of claim 29, further including:

keeping the one or more inputs connected to the primary operation circuitry at a low or ground voltage level for most of the time; and

setting them to a high voltage level only during relatively short pulses to indicate an upcoming removal of power from the primary operation circuitry.

31. An integrated circuit (IC) capable of reconfiguration while in a low-power state, the IC comprising:

a configuration memory configured to store configuration information for the IC;

a digital interface;

a digital input connected to the digital interface;

primary operation circuitry configured to perform one or more primary tasks and connected to the digital interface, the IC being configured to selectively remove at least a portion of its power from the primary operation circuitry during a low power mode; and

a first power manager connected to the primary operation circuitry, the digital input and the configuration memory and configured to

receive a set of one or more predefined digital signals over the digital input during the low power mode,

in response to the set of predefined digital signals, change the information stored in the configuration memory,

wherein changing the information stored in the configuration memory results in a change of the configuration of the IC;

wherein the primary operation circuitry includes a second power manager dedicated for managing power of the primary operation circuitry and configured to be powered down during the low power mode, and further configured to be powered up and perform power up operations on the primary operation circuitry in response to a signal from the first power manager.

32. The IC of claim 31, wherein the configuration memory includes core configuration memory.

33. The IC of claim 31, wherein the configuration memory includes I/O configuration memory.

34. The IC of claim 31, wherein the first power manager is configured to use small amount of power in relation to the primary operation circuitry.

35. The IC of claim 31, wherein the set of one or more predefined digital signals includes a payload portion and an error checking portion, and the first power manager is configured to check the payload portion based on the error checking portion before changing the information stored in the configuration memory.

36. An integrated circuit (IC) capable of communication with external devices while in a low-power state, the IC comprising:

an external device interface connected to one or more external devices;

a host interface connected to a host;

a configuration memory configured to store configuration information defining a configuration of the IC;

primary operation circuitry configured to perform one or more primary tasks and connected to the external device interface and the host interface, the IC being configured to selectively remove at least a portion of its power from the primary operation circuitry during a low power mode; and

a first power manager connected to the primary operation circuitry, and the external device and host interfaces, the first power manager configured to

receive a set of one or more predefined digital signals over the external device interface during the low power mode, and

in response to the set of predefined digital signals, change the information stored in the configuration memory, and send a signal to the host over the host interface,

wherein the primary operation circuitry includes a second power manager configured to be powered down during the low power mode, and further configured to be powered up and perform power up operations on the primary operation circuitry in response to a signal from the first power manager.

37. The IC of claim 36, wherein the host interface is an interrupt interface, and the signal sent to the host over the host interface is an interrupt signal.

38. The IC of claim 36, wherein the external devices are user interface devices.

39. The IC of claim 36, wherein the external devices comprise one or more devices selected from a group consisting of:

a keyboard, a button, a touch sensor, a proximity sensor, and a mouse.

40. The IC of claim 36, wherein the first power manager is configured to use small amount of power in relation to the primary operation circuitry.

41. The IC of claim 36, wherein the set of one or more predefined digital signals includes a payload portion and an error checking portion, and the first power manager is configured to check the payload portion based on the error checking portion before sending the signal to the host.

42. The IC of claim 36, wherein the first power manager is further configured to perform the following as part of sending a signal to the host:

generate a set of payload data;

generate a set of error checking data based on the payload data in accordance with a predefined error checking protocol; and

send the payload data along with the error checking data to the host.

43. An integrated circuit (IC) capable of responding to power-up messages while in a low-power state, the IC comprising:

a digital interface;

a digital input connected to the digital interface;

a configuration memory configured to store configuration information defining a configuration of the IC;

primary operation circuitry connected to the digital interface and configured to perform one or more primary tasks, during a normal power mode of operation of the IC, and to shut down operation during a low power mode of operation of the IC; and

a first power manager connected to the primary operation circuitry and the digital input, the first power manager configured to operate during the normal and low power modes of the IC, the first power manager configured to receive a set of one or more predefined digital signals over the digital input during the low power mode and, in response to the set of predefined digital signals, change the information stored in the configuration memory;

wherein the primary operation circuitry includes a second power manager configured to be powered down during the low power mode, and further configured to be powered up and perform power up operations on the primary operation circuitry in response to a signal from the first power manager, and

wherein at least a portion of the first power manager is in a disarmed state during a normal power mode.