High frequency switch circuit including gate bias resistances
First Claim
1. A high frequency switch circuit comprising:
- a first terminal;
a second terminal;
a bias terminal;
n (n is an integer more than one) number of transistors connected in series in an order from a first transistor to an nth transistor from said first terminal to said second terminal;
first to nth nodes connected to gates of said first to nth transistors; and
n number of resistance elements connected in series in an order from a first resistance element to an nth resistance element from said bias terminal to said nth node,wherein said first resistance element is connected between said bias terminal and said first node,wherein a kth resistance element (k=2 to n) is connected between said (k−
1)th node and said kth node, andwherein a gate current value of a kth transistor is identical to a gate current value of a (k−
1)th transistor.
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Accused Products
Abstract
N (n is an integer more than one) number of transistors are connected in series in an order from a first transistor to an nth transistor from a first terminal to a second terminal. First to nth nodes are connected to gates of the first to nth transistors. N number of resistance elements are connected in series in an order from a first resistance element to an nth resistance element from a bias terminal to the nth node. The first resistance element is connected between said bias terminal and said first node, and the kth resistance element (k=2 to n) is connected between the (k−1)th node and the kth node. Thus, a high frequency switch circuit can reduce an area of the whole gate bias resistances.
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Citations
12 Claims
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1. A high frequency switch circuit comprising:
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a first terminal; a second terminal; a bias terminal; n (n is an integer more than one) number of transistors connected in series in an order from a first transistor to an nth transistor from said first terminal to said second terminal; first to nth nodes connected to gates of said first to nth transistors; and n number of resistance elements connected in series in an order from a first resistance element to an nth resistance element from said bias terminal to said nth node, wherein said first resistance element is connected between said bias terminal and said first node, wherein a kth resistance element (k=2 to n) is connected between said (k−
1)th node and said kth node, andwherein a gate current value of a kth transistor is identical to a gate current value of a (k−
1)th transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor device comprising:
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n (n is an integer more than one) number of transistors connected in series; first to nth nodes connected to gates of said first to nth transistors, respectively; and n number of resistance elements connected in series in an order from a first resistance element to an nth resistance element, wherein said first resistance element is connected to said first node, and wherein a gate current value of one of said n number of transistors is equal to a gate current value of another one of said n number of transistors.
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Specification