Semiconductor device and method for manufacturing semiconductor device

• US 9,214,474 B2
• Filed: 06/28/2012
• Issued: 12/15/2015
• Est. Priority Date: 07/08/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Fan, Bo
• Application Number:
  US13/535,506
• Publication Number:
  US 20130009209A1
• Time in Patent Office: 1,265 Days
• Field of Search: 257/43, 257/40, 257/288, 257/192, 257/57, 257/E21.409, 257/E29.068, 257/E21.476, 438/104
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7782 with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer.

Claims

1. A semiconductor device comprising:

an oxide semiconductor stack layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor stack layer;

a gate insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the gate insulating film, the gate electrode layer overlapping with the oxide semiconductor stack layer,

wherein the second oxide semiconductor layer is between the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein a first mixed region whose composition is different from a composition of the first oxide semiconductor layer and a composition of the second oxide semiconductor layer is between the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein a second mixed region whose composition is different from the composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer is between the second oxide semiconductor layer and the third oxide semiconductor layer, and

wherein the third oxide semiconductor layer covers and is in contact with a side surface of the first oxide semiconductor layer and a top surface and a side surface of the second oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein an electron affinity of the second oxide semiconductor layer is higher than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein a region of the oxide semiconductor stack layer, which does not overlap with the source electrode layer or the drain electrode layer, has higher oxygen concentration than a region overlapping with the source electrode layer and the drain electrode layer.

4. The semiconductor device according to claim 1, wherein a region of the oxide semiconductor stack layer, which does not overlap with the gate electrode layer, contains a dopant.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.

6. A semiconductor device comprising:

an oxide semiconductor stack layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the oxide semiconductor stack layer;

a gate insulating film over the source electrode layer and the drain electrode layer; and

a gate electrode layer over the gate insulating film, the gate electrode layer overlapping with the oxide semiconductor stack layer,

wherein the second oxide semiconductor layer is between the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein a first mixed region whose composition is different from a composition of the first oxide semiconductor layer and a composition of the second oxide semiconductor layer is between the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein a second mixed region whose composition is different from the composition of the second oxide semiconductor layer and a composition of the third oxide semiconductor layer is between the second oxide semiconductor layer and the third oxide semiconductor layer,

wherein the third oxide semiconductor layer covers and is in contact with a side surface of the first oxide semiconductor layer and a top surface and a side surface of the second oxide semiconductor layer, and

wherein each of the source electrode layer and the drain electrode layer is in contact with a side surface of the third oxide semiconductor layer.

7. The semiconductor device according to claim 6, wherein an electron affinity of the second oxide semiconductor layer is higher than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

8. The semiconductor device according to claim 6, wherein a region of the oxide semiconductor stack layer, which does not overlap with the source electrode layer or the drain electrode layer, has higher oxygen concentration than a region overlapping with the source electrode layer and the drain electrode layer.

9. The semiconductor device according to claim 6, wherein a region of the oxide semiconductor stack layer, which does not overlap with the gate electrode layer, contains a dopant.

10. The semiconductor device according to claim 6, wherein the oxide semiconductor stacked layer comprises a crystal including a c-axis alignment.