Semiconductor apparatus

• US 9,224,823 B2
• Filed: 09/10/2013
• Issued: 12/29/2015
• Est. Priority Date: 03/22/2013
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawaguchi, Yusuke, Katoh, Shunsuke
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US14/023,339
• Publication Number:
  US 20140284711A1
• Time in Patent Office: 840 Days
• Field of Search: 257/331
• US Class Current: 1/1
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A semiconductor apparatus includes a drain region of a first-conductivity type, a drain electrode electrically coupled to the drain region, and a semiconductor layer of the first-conductivity type formed onto the drain region and having a first impurity concentration. The semiconductor apparatus further includes: a source region of the first-conductivity type formed on the semiconductor layer and having a second impurity concentration; a first source electrode electrically coupled to the source region; and a gate electrode formed via an insulating layer. The one end of the gate electrode is in a depth of the source region, and the other end is in a depth of the semiconductor layer or the drain region. A second source electrode is provided in the semiconductor layer under the gate electrodes via an insulating layer. A second spacing between the second source electrodes is larger than a first spacing between the gate electrodes.

Claims

1. A semiconductor apparatus comprising:

a drain region of a first conductivity type;

a drain electrode electrically coupled to the drain region;

a semiconductor layer of the first conductivity type formed onto the drain region, the semiconductor layer having a first impurity concentration;

a source region of the first conductivity type formed on the semiconductor layer, the source region having a second impurity concentration greater than the first impurity concentration;

a first source electrode electrically coupled to the source region;

a gate electrode formed via an insulating layer, the gate electrode having one end and another end, the one end being in a depth of the source region, and the other end being in a depth of the semiconductor layer or the drain region;

a second source electrode provided in the semiconductor layer under the gate electrodes via an insulating layer;

a first portion extending downward from a surface of the semiconductor layer to have a first depth, the first portion interiorly including the gate electrode and including the second source electrode under the gate electrode; and

a second portion extending downward from a surface of the semiconductor layer to have a second depth smaller than the first depth, the second portion interiorly including the gate electrode alone, wherein

a second spacing in between a plurality of the second source electrodes is configured larger than a first spacing in between a plurality of the gate electrodes.

2. The semiconductor apparatus according to claim 1, wherein

an upper layer portion of the semiconductor layer has a third impurity concentration smaller than the first impurity concentration.

3. The semiconductor apparatus according to claim 1, wherein

the second source electrode is embedded in a position under a part of the plurality of the gate electrodes.

4. The semiconductor apparatus according to claim 3, wherein

the second source electrode has a smaller width in a first direction than the gate electrodes.

5. The semiconductor apparatus according to claim 3, wherein

the second source electrode has a same width in a first direction as a width of the gate electrodes in the first direction.

6. The semiconductor apparatus according to claim 3, wherein

an upper layer portion of the semiconductor layer has a third impurity concentration smaller than the first impurity concentration.