Methods of forming epitaxial layers on a porous semiconductor layer

• US 9,245,760 B2
• Filed: 09/30/2010
• Issued: 01/26/2016
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mauder, Anton, Schulze, Hans-Joachim, Timme, Hans-Joerg, Hirler, Franz, Rodriguez, Francisco Javier Santos
• Primary Examiner(s): HSIEH, HSIN YI
• Application Number:
  US12/895,664
• Publication Number:
  US 20120080686A1
• Time in Patent Office: 1,944 Days
• Field of Search: 438/478, 257/E21.09
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first porous semiconductor layer over a top surface of a substrate;

forming a first epitaxial layer over the first porous semiconductor layer, wherein forming the first porous semiconductor layer comprises depositing an epitaxial layer and electrochemically etching at least a portion of the epitaxial layer, wherein depositing the epitaxial layer comprises forming a first layer having a first doping, and a second layer having a second doping different from the first layer;

forming stressor structures in the first epitaxial layer;

forming circuitry within and over the first epitaxial layer, wherein the circuitry is formed without completely oxidizing the first epitaxial layer;

forming a second porous semiconductor layer between the top surface of the substrate and the first porous semiconductor layer;

forming a second epitaxial layer between the first porous semiconductor layer and the second porous semiconductor layer;

thinning the substrate from a back surface to form an intermediate structure; and

dicing the intermediate structure to form singulated chips, wherein the thinning removes the second porous semiconductor layer, and wherein the thinning is stopped before reaching the first porous semiconductor layer.

2. The method of claim 1, wherein the substrate is a silicon wafer.

4. The method of claim 1, wherein the substrate comprises a silicon wafer.

3. A method of forming a semiconductor device, the method comprising:

forming a first porous semiconductor layer over a top surface of a substrate;

forming a first epitaxial layer over the first porous semiconductor layer;

forming stressor structures in the first epitaxial layer; and

forming circuitry within and over the first epitaxial layer, wherein the circuitry is formed without completely oxidizing the first epitaxial layer;

forming a second porous semiconductor layer between the top surface of the substrate and the first porous semiconductor layer;

forming a second epitaxial layer between the first porous semiconductor layer and the second porous semiconductor layer;

thinning the substrate from a back surface to form a remaining structure; and

dicing the remaining structure to form singulated chips, wherein the thinning removes the second porous semiconductor layer, and wherein the thinning is stopped before reaching the first porous semiconductor layer.

5. The method of claim 3,

wherein forming the first epitaxial layer comprises:

growing the first epitaxial layer along sidewalls and a top surface of the first porous semiconductor layer to form facets, and

merging the facets to close the pores in the first porous semiconductor layer.

6. The method of claim 3, wherein the substrate is a silicon wafer.

7. The method of claim 3, wherein forming the first porous semiconductor layer comprises:

depositing an additional epitaxial layer; and

electrochemically etching the additional epitaxial layer.

8. The method of claim 3, wherein forming the first porous semiconductor layer comprises depositing an additional epitaxial layer and electrochemically etching the additional epitaxial layer, and wherein depositing the additional epitaxial layer comprises forming a first layer having a first doping, and a second layer having a second doping different from the first layer.

9. The method of claim 5, wherein forming the second porous semiconductor layer comprises:

depositing an additional epitaxial layer; and

electrochemically etching the additional epitaxial layer.

10. The method of claim 3,

wherein forming the first epitaxial layer comprises:

growing the first epitaxial layer along sidewalls and a top surface of the first porous semiconductor layer to form facets, and

merging the facets to close the pores in the first porous semiconductor layer;

wherein forming the second porous semiconductor layer comprises depositing a third epitaxial layer and electrochemically etching the third epitaxial layer, and wherein depositing the third epitaxial layer comprises forming a first layer having a first doping, and a second layer having a second doping different from the first layer.

11. A method of forming a semiconductor device, the method comprising:

forming a buffer semiconductor layer having pores or openings over a top surface of a substrate, wherein forming the buffer semiconductor layer comprises etching using an anodic electrochemical etch process to form a porous region and exposing the porous region to a hydrogen anneal;

forming a compound semiconductor layer over the buffer semiconductor layer, wherein forming the compound semiconductor layer comprises;

growing the compound semiconductor layer along sidewalls and a top surface of the buffer semiconductor layer to form facets, and

merging the facets to close the pores in the buffer semiconductor layer;

forming circuitry within and over the compound semiconductor layer, wherein the circuitry is formed without completely oxidizing the compound semiconductor layer;

forming a porous semiconductor layer between the top surface of the substrate and the buffer semiconductor layer;

forming an epitaxial semiconductor layer between the buffer semiconductor layer and the porous semiconductor layer;

thinning the substrate from a back surface to form an remaining structure; and

dicing the remaining structure to form singulated chips, wherein the thinning removes the porous semiconductor layer, and wherein the thinning is stopped before reaching the buffer semiconductor layer.

12. The method of claim 11, wherein the circuitry comprises an optoelectronic device.

13. The method of claim 11, wherein the circuitry comprises a transistor.

14. The method of claim 11, wherein the substrate comprises a silicon wafer, and wherein the compound semiconductor layer comprises GaN.