Techniques for rate governing of a display data stream
First Claim
1. A method, comprising:
- determining, by a processor circuit, a target display data transmission rate for one or more displays;
generating, by a digital differential analyzer (DDA) communicatively coupled to the processor circuit, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate;
transmitting the one or more display data packets based on the actual display data transmission rate;
accumulating a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets, the display data packets comprising a display data packet stream, the display data packet stream comprising one or more display data transmission lanes;
receiving one or more display data source streams; and
processing the one or more display data source streams to form the display data packet stream, each of the one or more display data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data source streams.
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Accused Products
Abstract
Techniques for rate governing of a display data stream are described. In one embodiment, for example, an apparatus may comprise a processor circuit and a graphics management module comprising a differential analyzer. In some embodiments, the graphics management module may be operative on the processor circuit to determine a target display data transmission rate for one or more displays, determine, by the differential analyzer, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate, transmit the one or more display data packets based on the actual display data transmission rate, and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. Other embodiments are described and claimed.
10 Citations
26 Claims
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1. A method, comprising:
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determining, by a processor circuit, a target display data transmission rate for one or more displays; generating, by a digital differential analyzer (DDA) communicatively coupled to the processor circuit, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate; transmitting the one or more display data packets based on the actual display data transmission rate; accumulating a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets, the display data packets comprising a display data packet stream, the display data packet stream comprising one or more display data transmission lanes; receiving one or more display data source streams; and processing the one or more display data source streams to form the display data packet stream, each of the one or more display data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data source streams. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An article comprising a non-transitory computer-readable storage medium containing instructions that when executed by a processor cause a computing system to:
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determine a target display data transmission rate for one or more displays; determine, by a digital differential analyzer (DDA), an actual display data transmission rate for one or more display data packets based on the target display data transmission rate; monitor transmission of the one or more display data packets based on the actual display data transmission rate, the transmission of each of the one or more display data packets comprising; in an iterative loop, transmitting a next display data element comprised within a next display data slot in the display data packet, decrementing the DDA slot counter by one, and decrementing the rate governing slot counter by one, until the DDA slot counter is equal to zero; and when the rate governing slot counter is not less than one, iteratively transmitting a rate governing data element and decrementing the rate governing slot counter by one, until the rate governing slot counter is less than one; and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. - View Dependent Claims (10, 11, 12, 13, 14)
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15. An apparatus, comprising:
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a processor circuit; and a graphics management module comprising a digital differential analyzer (DDA), the graphics management module operative on the processor circuit to; determine a target display data transmission rate for one or more displays; generate, by the DDA, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate; transmit the one or more display data packets based on the actual display data transmission rate, the transmission of each of the one or more display data packets comprising; in an iterative loop, transmitting a next display data element comprised within a next display data slot in the display data packet, decrementing the DDA slot counter by one, and decrementing the rate governing slot counter by one, until the DDA slot counter is equal to zero; and when the rate governing slot counter is not less than one, iteratively transmitting a rate governing data element and decrementing the rate governing slot counter by one, until the rate governing slot counter is less than one; and accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A system, comprising:
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a processor circuit; an audio device communicatively coupled to the processor circuit; and a graphics management module comprising a digital differential analyzer (DDA), the graphics management module operative on the processor circuit to; determine a target display data transmission rate for one or more displays; generate, by the DDA, an actual display data transmission rate for one or more display data packets based on the target display data transmission rate; transmit the one or more display data packets based on the actual display data transmission rate; accumulate a difference between the actual display data transmission rate and the target display data transmission rate for the one or more display data packets; receive one or more display data source streams at a first data rate defined by a display data source stream clock signal, the first data rate differing from a display data consumption rate of the one or more displays; process the one or more display data source streams to form the display data packet stream, each of the one or more display data transmission lanes in the display data packet stream corresponding to a different one of the one or more display data source streams; and transmit the display data packet stream at a second data rate that differs from the first data rate and matches the display data consumption rate of the one or more displays. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification