Semiconductor device, method for fabricating the same, and memory system including the semiconductor device

• US 9,312,376 B2
• Filed: 01/15/2014
• Issued: 04/12/2016
• Est. Priority Date: 06/13/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Young-Tak, Son, Ho-Sung, Won, Seok-Jun, Yi, Ji-Hye, Lee, Chul-Woong, Kim, Kook-Tae
• Primary Examiner(s): Le, Toan
• Application Number:
  US14/155,651
• Publication Number:
  US 20140369115A1
• Time in Patent Office: 818 Days
• Field of Search: 365/182, 257/E21.54, 257/21.158, 257/21.585, 257/21.495
• US Class Current: 1/1
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.

Claims

1. A semiconductor device, comprising:

an interlayer insulating layer formed on a substrate and including a trench;

a gate electrode formed in the trench and including a first metal layer and a second metal layer, the first metal layer formed along a side and a bottom surface of the trench and the second metal layer filling a space formed by the first metal layer;

a gate dielectric film formed between the substrate and the gate electrode;

a first gate spacer including silicon nitride formed on the sidewall of the gate electrode and the gate dielectric film;

a second gate spacer formed on the first gate spacer and having a dielectric constant lower than the dielectric constant of silicon nitride;

a third spacer formed on the second gate spacer; and

an elevated source/drain formed in a recess formed in the substrate and including SiGe,

wherein the first gate spacer directly contacts the gate dielectric film, and a top surface of the elevated source/drain is higher than a top surface of the gate dielectric film under the gate electrode.

2. The semiconductor device of claim 1, wherein the second gate spacer has a dielectric constant which is higher than that of silicon oxide.

3. The semiconductor device of claim 2, wherein the second gate spacer includes SiOCN or SiOC.

4. The semiconductor device of claim 3, wherein the dielectric constant of the second gate spacer has a value between 4 and 6, and the first and the second gate spacers have bottom portions respectively protrude away from the sidewall of the gate electrode and the gate dielectric film.

5. The semiconductor device of claim 1, wherein the third gate spacer includes silicon nitride.

6. The semiconductor device of claim 1, wherein a top surface of the interlayer insulating layer and a top surface of the gate electrode are disposed on the same plane.

7. The semiconductor device of claim 1, wherein the gate dielectric film includes hafnium oxide.

8. The semiconductor device of claim 1, wherein the first metal layer includes TiN.

9. The semiconductor device of claim 8, wherein the second metal layer includes Al.

10. A semiconductor device, comprising:

an interlayer insulating layer formed on a substrate and including a trench;

a gate electrode formed in the trench and including a first metal layer and a second metal layer, the first metal layer formed along a side and a bottom surface of the trench and the second metal layer filling a space formed by the first metal layer;

a gate dielectric film formed between the substrate and the gate electrode;

a first gate spacer including silicon nitride formed on the sidewall of the gate electrode and the gate dielectric film, the first gate spacer having a bottom portion protruding away from the sidewall of the gate electrode;

a second gate spacer formed on the first gate spacer and having a dielectric constant lower than the dielectric constant of silicon nitride;

a third spacer formed on the second gate spacer; and

an elevated source/drain formed in a recess formed in the substrate and including SiGe,

wherein the first gate spacer directly contacts the gate dielectric film, and a top surface of the elevated source/drain is higher than a top surface of the gate dielectric film under the gate electrode.

11. The semiconductor device of claim 10, wherein the second gate spacer has a dielectric constant which is higher than that of silicon oxide.

12. The semiconductor device of claim 11, wherein the second gate spacer includes SiOCN or SiOC.

13. The semiconductor device of claim 12, wherein the dielectric constant of the second gate spacer has a value between 4 and 6, and the first and the second gate spacers respectively have L shapes.

14. The semiconductor device of claim 10, wherein the third gate spacer includes silicon nitride.

15. The semiconductor device of claim 10, wherein a top surface of the interlayer insulating layer and a top surface of the gate electrode are disposed on the same plane.

16. The semiconductor device of claim 10, wherein the gate dielectric film includes hafnium oxide.

17. The semiconductor device of claim 10, wherein the first metal layer includes TiN.

18. The semiconductor device of claim 17, wherein the second metal layer includes Al.