Method of operating incrementally programmable non-volatile memory
First Claim
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1. A method of programming a non-volatile device having memory cells each adapted to represent a logic state, and each including a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the method comprising:
- setting all the non-volatile device memory cells to a first reference state corresponding to a first logic value represented by a first threshold voltage Vt1;
programming selected ones of the non-volatile device memory cells to a second reference state corresponding to a second logic value represented by a second threshold voltage Vt2, where Vt2>
Vt1;
resetting all the non-volatile device memory cells to a third reference state corresponding to said first logic value and represented by a third threshold voltage Vt3, where Vt3>
=Vt2;
reprogramming selected ones of the non-volatile device memory cells to a fourth reference state corresponding to said second logic value represented by a fourth threshold voltage Vt4, where Vt4>
Vt3;
wherein both programming and erasing a target logic state of the non-volatile device is performed by addition of electrons to the floating gate;
and wherein each cell is reset to a common state prior to programming or reprogramming.
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Abstract
An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a Vt representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.
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Citations
14 Claims
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1. A method of programming a non-volatile device having memory cells each adapted to represent a logic state, and each including a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the method comprising:
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setting all the non-volatile device memory cells to a first reference state corresponding to a first logic value represented by a first threshold voltage Vt1; programming selected ones of the non-volatile device memory cells to a second reference state corresponding to a second logic value represented by a second threshold voltage Vt2, where Vt2>
Vt1;resetting all the non-volatile device memory cells to a third reference state corresponding to said first logic value and represented by a third threshold voltage Vt3, where Vt3>
=Vt2;reprogramming selected ones of the non-volatile device memory cells to a fourth reference state corresponding to said second logic value represented by a fourth threshold voltage Vt4, where Vt4>
Vt3;wherein both programming and erasing a target logic state of the non-volatile device is performed by addition of electrons to the floating gate; and wherein each cell is reset to a common state prior to programming or reprogramming. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of programming a CMOS logic process compatible non-volatile device having a memory array with memory cells each adapted to represent a logic state, and each including a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the method comprising:
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setting all the non-volatile device memory cells in the memory array to a first reference state corresponding to a first logic value represented by a first threshold voltage Vt1; programming selected ones of the non-volatile device memory cells in the memory array to a second reference state corresponding to a second logic value represented by a second threshold voltage Vt2 using hot carrier injection, where Vt2>
Vt1;resetting all the non-volatile device memory cells in the memory array at predetermined intervals to a third reference state corresponding to said first logic value and represented by a third threshold voltage Vt3 using hot carrier injection, where Vt3>
=Vt2;wherein said resetting is performed as part of an automated security operation and/or degradation refresh operation in the non-volatile memory device; reprogramming selected ones of the non-volatile device memory cells in the memory array after said predetermined intervals to a fourth reference state corresponding to said second logic value represented by a fourth threshold voltage Vt4 using hot carrier injection, where Vt4>
Vt3;wherein both programming and erasing a target logic state of the non-volatile device is performed by addition of hot electrons to the floating gate; and wherein each cell in the memory cell array is set or reset to a common state prior to programming or reprogramming. - View Dependent Claims (13, 14)
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Specification