METHOD OF OPERATING INCREMENTALLY PROGRAMMABLE NON-VOLATILE MEMORY
First Claim
Patent Images
1. In a method of programming a non-volatile device having memory cells each adapted to represent a logic state, and each including a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the improvement compromising:
- setting all the non-volatile device memory cells to a first reference state corresponding to a first logic value represented by a first threshold voltage Vt1;
programming selected ones of the non-volatile device memory cells to a second reference state corresponding to a second logic value represented by a second threshold voltage Vt2, where Vt2>
Vt1;
resetting all the non-volatile device memory cells to a third reference state corresponding to said first logic value and represented by a third threshold voltage Vt3, where Vt3>
=Vt2;
reprogramming selected ones of the non-volatile device memory cells to a fourth reference state corresponding to said second logic value represented by a fourth threshold voltage Vt4, where Vt4>
Vt3;
wherein both writing and erasing a target logic state of the programmable non-volatile device is performed by addition of electrons to the floating gate.and wherein each cell is reset to a common state prior to programming or reprogramming.
1 Assignment
0 Petitions
Accused Products
Abstract
An array of programmable non-volatile devices, such as a nominal OTP cell, is operated such that a Vt representing a particular binary logic state is changed over time. This allows for re-programming and emulating a few times or multi-time programmable device.
5 Citations
9 Claims
-
1. In a method of programming a non-volatile device having memory cells each adapted to represent a logic state, and each including a floating gate, a control gate, a source region, a drain region, and a channel coupling said source region and said drain region, the improvement compromising:
-
setting all the non-volatile device memory cells to a first reference state corresponding to a first logic value represented by a first threshold voltage Vt1; programming selected ones of the non-volatile device memory cells to a second reference state corresponding to a second logic value represented by a second threshold voltage Vt2, where Vt2>
Vt1;resetting all the non-volatile device memory cells to a third reference state corresponding to said first logic value and represented by a third threshold voltage Vt3, where Vt3>
=Vt2;reprogramming selected ones of the non-volatile device memory cells to a fourth reference state corresponding to said second logic value represented by a fourth threshold voltage Vt4, where Vt4>
Vt3;wherein both writing and erasing a target logic state of the programmable non-volatile device is performed by addition of electrons to the floating gate. and wherein each cell is reset to a common state prior to programming or reprogramming. - View Dependent Claims (2, 3)
-
-
4. A method of dividing a total capacity (Ct) of an non-volatile memory array containing M cells and N distinct program levels into P distinct periods, the method compromising:
-
performing a first program operation in a 1st period of the P distinct periods to store logical data in the M cells of the array using at least two (2) or more separate program levels {PVt1, PVt2} of the N distinct program levels; performing a second program operation in a subsequent 2nd period of the P distinct periods to store logical data in the M cells of the array using at least (2) separate program levels {PVt3, PVt4} of the N distinct program levels, wherein at least one of {PVt3, PVt4} is different from and greater than {PVt1, PVt2}; wherein data in the M cells is reset to a common initialized state by a reset operation between the first and second program operations.
-
-
6. The method of claim 10 wherein a threshold value of programmed cells is increased during each subsequent program operation in the P distinct periods.
-
9. A method of erasing or resetting an array of one-time programmable (OTP) non-volatile memory cells where each of such cells in the array is adapted to store data through injection of hot carriers into a floating gate, the method comprising:
-
providing an original target highest threshold voltage for programming the cells; further injecting electrons to all the OTP memory cells, wherein the threshold voltage of every cell in the array is substantially same as the original highest threshold voltage. - View Dependent Claims (5, 7, 8)
-
Specification