Integrated circuit including circuits driven in different voltage domains
First Claim
1. An integrated circuit comprising:
- a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level; and
a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level, the memory circuit comprising a circuit configured to interface with the logic circuit,wherein the circuit is configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level,wherein the circuit comprises a clocked gate configured to be driven by the second power supply voltage level and configured to generate the output signal of the circuit in response to the signal and a clock signal,wherein the circuit further comprises an interface circuit configured to receive the signal having the first power supply voltage level, andwherein the interface circuit comprises;
a first circuit unit connected between the second power supply voltage and a first node, the first circuit unit configured to be supplied with power at the second power supply voltage level according to the output signal of the clocked gate, and configured to receive the signal;
a second circuit unit connected between the second power supply voltage and the first node, the second circuit unit configured to receive the clock signal;
a third circuit unit connected between the first node and a ground voltage having a ground voltage level, the third circuit unit configured to receive the signal and the clock signal; and
a fourth circuit unit configured to be driven by the second power supply voltage, to receive a signal of the first node, and to output an output signal of a second circuit area.
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Accused Products
Abstract
Provided is an integrated circuit including circuits driven in different voltage domains. The integrated circuit includes a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level, and a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level. The memory circuit includes a circuit configured to interface with the logic circuit, configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level. The first power supply voltage corresponds to a first voltage domain, and the second power supply voltage corresponds to a second voltage domain.
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Citations
24 Claims
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1. An integrated circuit comprising:
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a logic circuit configured to be driven by a first power supply voltage having a first power supply voltage level; and a memory circuit configured to be driven by a second power supply voltage having a second power supply voltage level different from the first power supply voltage level, the memory circuit comprising a circuit configured to interface with the logic circuit, wherein the circuit is configured to be supplied with power at the second power supply voltage level in response to an output signal, and configured to shift a level of a signal having the first power supply voltage level received from the logic circuit to the second power supply voltage level, wherein the circuit comprises a clocked gate configured to be driven by the second power supply voltage level and configured to generate the output signal of the circuit in response to the signal and a clock signal, wherein the circuit further comprises an interface circuit configured to receive the signal having the first power supply voltage level, and wherein the interface circuit comprises; a first circuit unit connected between the second power supply voltage and a first node, the first circuit unit configured to be supplied with power at the second power supply voltage level according to the output signal of the clocked gate, and configured to receive the signal; a second circuit unit connected between the second power supply voltage and the first node, the second circuit unit configured to receive the clock signal; a third circuit unit connected between the first node and a ground voltage having a ground voltage level, the third circuit unit configured to receive the signal and the clock signal; and a fourth circuit unit configured to be driven by the second power supply voltage, to receive a signal of the first node, and to output an output signal of a second circuit area. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A decoder comprising:
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a logic gate configured to decode a plurality of first input signals having a first power supply voltage level and generate a first output signal at an output node, the first output signal having a second power supply voltage level different from the first power supply voltage level; and an inverter configured to invert the first output signal and generate a second output signal at the second power supply voltage level, wherein the decoder is configured to receive a first clock signal configured to control precharging the output node at a first logic level of the first clock signal and evaluate the output node at a second logic level of the first clock signal, and wherein the second output signal is received at the logic gate. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A memory comprising:
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an address decoder configured to decode a plurality of address input signals at a first power supply voltage level and generate a first address decoding signal at an output node at a second power supply voltage level different from the first power supply voltage level; and an inverter configured to invert the first address decoding signal and generate a second address decoding signal at the second power supply voltage level, wherein the memory is configured to receive a first clock signal configured to control precharging the output node at a first phase of the first clock signal and evaluate the output node at a second phase of the first clock signal, and wherein the second address decoding signal is received at a logic gate. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method of processing data by an integrated circuit comprising a logic circuit and a memory circuit, the method comprising:
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generating, by the logic circuit, control signals having a first power supply voltage level which are used to control the memory circuit, and transmitting the control signals to the memory circuit; shifting, by the memory circuit, levels of the controls signals to a second power supply voltage level which is different from the first power supply voltage level; and performing, by the memory circuit, read or write operations according to the control signals having the shifted levels, wherein the shifting comprises driving a clocked gate comprised in the memory circuit by the second power supply voltage level such that the clocked gate generates, in response to a clock signal, an output signal to be used by the memory circuit during the shifting, wherein the method further comprises; receiving, by an interface circuit comprised in the memory circuit, the control signals having the first power supply voltage level, supplying a first circuit unit, which is comprised in the interface circuit and connected between a second power supply voltage having the second power supply voltage level and a first node, with power at the second power supply voltage level according to the output signal of the clocked gate, receiving, by the first circuit unit, the control signals having the first power supply voltage level, receiving, by a second circuit unit which is comprised in the interface circuit and connected between the second power supply voltage and the first node, the clock signal, receiving, by a third circuit unit which is comprised in the interface circuit and connected between the first node and a ground voltage having a ground voltage level, the control signals having the first power supply voltage level and the clock signal, driving a fourth circuit unit, which is comprised in the interface circuit, by the second power supply voltage, receiving, by the fourth circuit unit, a signal of the first node, and outputting, by the fourth circuit, an output signal of a second circuit area. - View Dependent Claims (22, 23, 24)
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Specification