Memory channel that supports near memory and far memory access

• US 9,342,453 B2
• Filed: 09/30/2011
• Issued: 05/17/2016
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Nale, Bill, Ramanujan, Raj K., Swaminathan, Muthukumar P., Thomas, Tessil, Polepeddi, Taarinya
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US13/977,603
• Publication Number:
  US 20140040550A1
• Time in Patent Office: 1,691 Days
• Field of Search: 711118-122, 711/141, 710/1
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2024 Rewritable memory not requiring erasing, e.g. resistive or ferroelectric RAM
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Claims

1. A method performed by logic circuitry disposed on a card having a connector to plug into a memory channel that supports near memory cache accesses and far memory accesses, comprising:

receiving from said memory channel a first tag component of a target address of a read request transaction being processed by a host that is coupled to said memory channel;

receiving a second tag component of an address of a cache line read from a near memory cache in response to said read request transaction; and

,

comparing said first and second tag components to determine if said cache line corresponds to a cache hit or a cache miss.

2. The method of claim 1 further comprising

performing at least one of the following in response to detecting that a cache miss has occurred:

automatically reading a desired cache line from far memory;

detecting that a dirty bit of said cache line read from near memory is set and automatically writing said cache line read from said near memory into far memory.

3. The method of claim 1 wherein after said reading of said desired cache line from far memory said logic circuitry further performs an ECC calculation on data of said desired cache line.

4. The method of claim 1 wherein said near memory cache is implemented with DRAM technology and said far memory is implemented with PCM technology.

5. The method of claim 1 wherein said near memory cache resides on said card.

6. The method of claim 1 further comprising

performing the following in response to detecting that a cache miss has occurred:

receiving from said host an identifier of said read request transaction and presenting said identifier of said read request transaction on said channel as part of a communication on said channel that transports data of said cache line read from far memory to said host.

7. The method of claim 1 wherein said first tag component is received with a first read request presented on said channel by said host according to a first channel protocol used for accessing said near memory.

8. The method of claim 7 wherein said second tag component is received with a second read request presented on said channel by said host according to a second channel protocol used for accessing said far memory.

9. A semiconductor chip, comprising:

an interface to a memory channel;

a read buffer to hold a far memory read request received from said memory channel;

logic circuitry to detect a cache miss of a cache line read from a near memory in response to a near memory read request issued on said memory channel, said near memory a cache for said far memory, said logic circuitry to additionally perform at least one of the following in response thereto;

initiate a read of a desired cache line from said far memory, said desired cache line containing data sought by a transaction that caused said near memory read request to be issued on said memory channel;

detect that a dirty bit of said cache line read from near memory is set and automatically writing said cache line read from said near memory into far memory.

10. The semiconductor chip of claim 9 wherein said logic circuitry receives from said first interface both tag information of an address of said cache line read from near memory and tag information of said transaction'"'"'s address.

11. The semiconductor chip of claim 9 wherein said logic circuitry includes a second interface distinct from said first interface to couple to said far memory, and wherein said semiconductor chip to receive through said first interface tag information of said transaction'"'"'s address.

12. The semiconductor chip of claim 9 further comprising ECC logic to calculate ECC information for said cache line read from said near memory and/or said cache line written into said far memory.

13. The semiconductor chip of claim 9 further comprising first register space to store a first tag component of said transaction'"'"'s address, and, second register space to store a second tag component of an address of said cache line read from said near memory, said second tag component embedded with said cache line read from said near memory.

14. The semiconductor chip of claim 9 wherein said near memory is implemented with DRAM and said far memory component is implemented with PCM.

15. The semiconductor chip of claim 14 wherein said semiconductor chip further comprises wear out leveling algorithm logic circuitry for said PCM far memory.

16. The semiconductor chip of claim 14 wherein said semiconductor chip further comprises a write request buffer to hold write requests to said far memory, and, a read request buffer to hold read requests to said far memory.