Methods and systems for chemical mechanical polish and clean

• US 9,449,841 B2
• Filed: 12/19/2013
• Issued: 09/20/2016
• Est. Priority Date: 12/19/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Ying-Liang, Suen, Shich-Chang, Liu, Chi-Jen, Wu, Li-Chieh, Chen, Liang-Guang, Yen, Ming-Liang
• Primary Examiner(s): Oh, Jaehwan
• Application Number:
  US14/134,914
• Publication Number:
  US 20150179432A1
• Time in Patent Office: 1,006 Days
• US Class Current: 1/1
• CPC Class Codes: B24B 37/20 Lapping pads for working plane surfaces
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/67051 using mainly spraying means, e.g. nozzles
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions; performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and cleaning the planarized MG layer using a O₃/DIW solution including ozone gas (O₃) dissolved in deionized water (DIW). The MG layer is formed on the ILD regions.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions, the MG layer being formed on the ILD regions;

performing a chemical mechanical polishing (CMP) process using a CMP system to planarize the MG layer and the ILD regions; and

cleaning the planarized MG layer using a O₃/DIW solution including ozone gas (O₃) dissolved in deionized water (DIW), wherein an O₃/DIW generator is coupled to a cleaning unit of the CMP system to supply the O₃/DIW solution, wherein the cleaning unit includes a spray nozzle coupled to the O₃/DIW generator, and wherein the cleaning the planarized MG layer includes cleaning a surface of the semiconductor structure using the spray nozzle further coupled to a megasonic generator configured to provide an oscillation to the O₃/DIW solution to form an O₃/DIW fog to be sprayed from the spray nozzle to the surface of the semiconductor structure.

2. The method of claim 1, further comprising:

forming a metal oxide layer on the MG layer simultaneously with the cleaning of the planarized MG layer.

3. The method of claim 1, wherein the cleaning the planarized MG layer using the O₃/DIW solution comprises removing organic residue from CMP slurry by a reaction:

—

CH₂+3O₃→

CO₂+3O₂+3H₂O

the organic residue including a functional group —

CH₂.

4. The method of claim 1, wherein the O₃/DIW generator is coupled to a polishing unit of the CMP system, and wherein the cleaning the planarized MG layer includes buffing a surface of the semiconductor structure using a buffing pad and the O₃/DIW solution in the polishing unit, the polishing unit including a pipeline coupled to the O₃/DIW generator to supply the O₃/DIW solution to the buffing pad.

5. The method of claim 1, wherein the cleaning unit includes a water tank coupled to the O₃/DIW generator, and wherein the cleaning the planarized MG layer includes cleaning a surface of the semiconductor structure in the water tank further coupled to a megasonic generator configured to provide an oscillation to the O₃/DIW solution contained in the water tank.

6. The method of claim 1, wherein the cleaning unit includes:

a brush configured to scrub a surface of the semiconductor structure; and

another spray nozzle coupled to the O₃/DIW generator,

wherein the cleaning the planarized MG layer includes scrubbing the surface of the semiconductor structure using the brush and the O₃/DIW solution sprayed from the another spray nozzle.

7. The method of claim 1, wherein the cleaning the planarized MG layer includes:

buffing a surface of the semiconductor structure using a buffing pad and the O₃/DIW solution in a polishing unit, the polishing unit including a pipeline coupled to the O₃/DIW generator configured to supply the O₃/DIW solution to the buffing pad; and

cleaning the surface of the semiconductor structure in a water tank coupled to the megasonic generator configured to provide an oscillation to the O₃/DIW solution contained in the water tank, the water tank coupled to the O₃/DIW generator configured to supply the O₃/DIW solution to the water tank.

8. The method of claim 1, wherein the cleaning the planarized MG layer includes:

scrubbing the surface of the semiconductor structure using a brush and the O₃/DIW solution sprayed from the spray nozzle.

9. The method of claim 1, wherein a pH value of the O₃/DIW solution is in a range from 4 to 9.

10. The method of claim 1, wherein a concentration of the O₃ dissolved in the O₃/DIW solution is in a range from 5 ppm to 70 ppm.

11. The method of claim 1, further comprising:

drying the cleaned semiconductor structure;

depositing an etch stop layer (ESL) over the ILD regions and the MG layer; and

forming a contact hole through the ESL and the ILD regions.

15. The method of claim 1, wherein a temperature of the O₃/DIW solution is in a range from 15°

C. to 60°

C.

16. The method of claim 1, wherein the O₃/DIW solution is applied to the planarized MG layer for 5 to 240 seconds.

12. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor structure including a metal gate (MG) layer formed to fill in a trench between two adjacent interlayer dielectric (ILD) regions;

performing a chemical mechanical polishing (CMP) process to planarize a first surface of the MG layer and the ILD regions;

buffing the first surface with a buffing pad using a O₃/DIW solution that includes ozone gas (O₃) dissolved in deionized water (DIW); and

after the buffing of the first surface, cleaning the first surface, wherein the cleaning of the first surface includes spraying an oscillating O₃/DIW fog onto the first surface.

13. The method of claim 12, wherein the cleaning of the first surface further includes immersing the semiconductor structure in a water tank provided with megasonic-energized O₃/DIW solution.

14. The method of claim 12, wherein the cleaning of the first surface includes spraying a cleaning solution onto the first surface while scrubbing the first surface with a brush.

17. The method of claim 14, wherein the spraying of the cleaning solution and the spraying of the oscillating O₃/DIW fog use two different nozzles.

18. The method of claim 17, wherein the two different nozzles are coupled to a same O₃/DIW generator, and the cleaning solution is also the O₃/DIW solution.

19. The method of claim 18, wherein the buffing of the first surface includes receiving the O₃/DIW solution from the O₃/DIW generator.