Semiconductor device with enhanced mobility and method

• US 9,450,091 B2
• Filed: 10/02/2014
• Issued: 09/20/2016
• Est. Priority Date: 06/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon M., Hossain, Zia, Huang, Kirk K., Padmanabhan, Balaji, Robb, Francine Y., Venkatraman, Prasad
• Primary Examiner(s): JOHNSON, CHRISTOPHER A
• Application Number:
  US14/504,527
• Publication Number:
  US 20150054068A1
• Time in Patent Office: 719 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

Claims

1. A method of forming a semiconductor device comprising:

providing a region of semiconductor material having a trench extending from a major surface and having an isolated shield electrode structure in a lower portion of the trench and a gate dielectric layer adjacent sidewalls of the trench;

forming conductive spacers adjacent the gate dielectric layer in the trench, the conductive spacers configured as part of a gate electrode structure;

forming a stress inducing structure within the trench and interposed between the conductive spacers, wherein the stress inducing structure and the conductive spacers comprise different materials; and

thereafter forming a conductive layer adjacent the stress inducing layer and interposed between the conductive spacers, the conductive layer configured as another part of the gate electrode structure.

2. The method of claim 1 further comprising forming a stress inducing layer along portions of the conductive spacers.

3. The method of claim 2, wherein forming the stress inducing layer comprises forming a layer comprising a silicide.

4. The method of claim 3, wherein forming the stress inducing structure includes forming a stress inducing structure comprising a dielectric.

5. The method of claim 1, wherein forming the conductive spacers comprises:

forming a doped polycrystalline semiconductor layer; and

removing a lower portion of the doped polycrystalline semiconductor layer adjacent the insulated shield electrode to form doped polycrystalline spacers.

6. The method of claim 1, wherein forming the stress inducing structure includes recessing the stress inducing structure within the trench.

7. The method of claim 1, wherein forming the stress inducing structure includes forming the stress inducing structure comprising a conductive material.

8. The method of claim 1, wherein forming the stress inducing structure includes forming the stress inducing structure comprising a silicide material.

9. A method for forming an insulating gate field effect transistor structure having enhanced mobility comprising:

providing a region of semiconductor material having a first conductivity type, a first major surface, and a second major surface opposing the first major surface, where the region of semiconductor material at the second major surface is configured as a drain region;

providing a trench structure within the region of semiconductor material comprising;

a shield electrode in a lower portion of a trench, where the shield electrode is separated from the region of semiconductor material by a first dielectric layer;

a gate electrode in an upper portion of the trench, where the gate electrode is separated from the region of semiconductor material by a second dielectric layer and separated from the shield electrode by a third dielectric layer; and

a first region within the gate electrode and comprising a silicide material, wherein the a first region within the gate electrode and comprising a silicide material, wherein the first region is recessed within the trench structure so that no portion of the first region overlaps onto the first major surface and a portion of the first region is provided between the gate electrode and the shield electrode;

providing a body region having a second conductivity type opposite to the first conductivity type in the region of semiconductor material, where the body region and the trench region are adjacent, and where the gate electrode is configured to form a channel region within the body region; and

providing a source region of the first conductivity type in the body region, the source region having a first side adjacent to the trench structure and a second side opposite to the first side,

wherein the first region is configured to propagate stress within the region of semiconductor material adjacent to the trench structure to provide the enhanced mobility.

10. The method of claim 9 further comprising providing a second region within the shield electrode and comprising a material configured to propagates stress within a drift region of the structure to provide the enhanced mobility.

11. The method claim 10, where providing the second region comprises providing the second region comprising a silicide.

12. The method of claim 11 further comprising:

providing a third region overlying the shield electrode; and

providing a fourth region overlying the gate electrode, wherein both the third and fourth regions comprise a material configured to propagate stress within the region of semiconductor material adjacent to the trench structure.

13. The method of claim 9 further comprising a providing second region adjacent to the second side of the source region and comprising a material that propagates stress in proximity to a source end of the channel region.