Method and system for coordinated data execution using a primary graphics processor and a secondary graphics processor

• US 9,471,952 B2
• Filed: 02/05/2013
• Issued: 10/18/2016
• Est. Priority Date: 03/14/2003
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Diercks, Dwight D., De Waal, Abraham B.
• Primary Examiner(s): Richer, Joni
• Application Number:
  US13/759,401
• Publication Number:
  US 20140055465A1
• Time in Patent Office: 1,351 Days
• Field of Search: 345/502, 345/542, 345/503, 345/505, 345/501, 345/530, 345/531, 345/536
• US Class Current: 1/1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.

Claims

1. A system for coordinated operation of graphics processors, said system comprising:

a first graphics processor coupled to a local graphics memory via a local bus;

a second graphics processor communicatively coupled to a system memory via a memory controller, wherein the memory controller provides an interconnection between the system memory and the second graphics processor; and

a graphic bus coupling the first graphics processor and the memory controller, wherein coordinated operation of the first graphics processor and the second graphics processor is based on a characteristic of the graphic bus.

2. The system of claim 1, wherein a workload between the first graphics processor and the second graphics processor is shared.

3. The system of claim 1, wherein the first graphics processor and the second graphics processor are communicatively coupled through the graphic bus.

4. The system of claim 3, further comprising a plurality of high speed connection busses wherein said plurality of high speed connection busses connect the memory controller, the system memory, the second graphics processor, and a central processor, and wherein the plurality of high speed connection busses are configured to provide greater data transfer bandwidth compared to the graphic bus.

5. The system of claim 4, wherein the local bus is a high performance bus configured to provide greater data transfer bandwidth compared to the plurality of high speed connection busses.

6. A system for coordinated data execution and coordinated graphics processing, said system comprising:

a primary graphics processor coupled to a local graphics memory via a first local bus;

a secondary graphics processor coupled to a system memory via a second local bus, wherein the second local bus provides a higher communication bandwidth compared to the first local bus;

a local graphics bus configured to couple the primary graphics processor and the secondary graphics processor; and

a graphics driver configured to split a processing workload between the primary graphics processor and the secondary graphics processor, wherein the split of the processing workload between the primary graphics processor and the secondary graphics processor is based on a characteristic of the local graphics bus.

7. The system of claim 6, wherein the primary graphics processor is communicatively connected to the system memory via the local graphics bus, and wherein the local graphics bus provides a lower bandwidth connection compared to the first local bus and the second local bus.

8. The system of claim 6, wherein the secondary graphics processor is integrated with a system memory controller.

9. The system of claim 6, wherein the secondary graphics processor has a faster access to the system memory compared to the primary graphics processor.

10. The system of claim 6, wherein the secondary graphics processor has a greater communications bandwidth with a central processor compared to the primary graphics processor.

11. The system of claim 6, wherein the primary graphics processor is a card-mounted graphics processor configured to connect to an accelerated graphics port (AGP) slot of the graphics bus.

12. The system of claim 6, wherein the secondary graphics processor is configured to perform graphics rendering operations that occur in a first portion of a graphics pipeline, wherein the operations comprise transform, lighting, occlusion culling, back face culling, view frustum culling, or clipping.

13. The system of claim 6, wherein the secondary graphics processor processes commands from a processing thread that is different from the primary graphics processor.

14. The system of claim 6, wherein the secondary graphics processor is a smaller processor compared to the primary graphics processor.

15. The system of claim 6, wherein the primary graphics processor performs graphics rendering operations that occur in a second portion of a graphics rendering pipeline, wherein the graphics rendering operations comprise lighting, bump, mapping, and texture mapping.

16. The system of claim 6, wherein the secondary graphics processor is configured to use a portion of the system memory as a dedicated local memory.

17. A method for coordinated data execution and coordinated operation of graphics processors, said method comprising:

communicating data between a primary graphics processor and a local graphics memory via a first local bus;

communicating data between a secondary graphics processor and a system memory via a second local bus, wherein the secondary graphics processor utilizes a higher communications bandwidth with the system memory compared to a communications bandwidth of the primary graphics processor with the local graphics memory;

communicating data between the primary graphics processor and the secondary graphics processor via a local graphics bus; and

splitting a processing workload between the primary graphics processor and the secondary graphics processor via a graphics driver, wherein the splitting of the processing workoad between the primary graphics processor and the secondary graphics processor is based on a characteristic of the local graphics bus.

18. The method of claim 17, wherein the primary graphics processor is communicatively coupled to the system memory.

19. The method of claim 17, wherein the workload between the primary graphics processor and the secondary graphics processor is split based on the amount of data to be transferred across the local graphics bus.